Home
last modified time | relevance | path

Searched refs:SRII (Results 1 – 25 of 29) sorted by relevance

12

/linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dce/
A Ddce_clock_source.h60 SRII(PHASE, DP_DTO, 0),\
61 SRII(PHASE, DP_DTO, 1),\
62 SRII(PHASE, DP_DTO, 2),\
63 SRII(PHASE, DP_DTO, 3),\
64 SRII(PHASE, DP_DTO, 4),\
65 SRII(PHASE, DP_DTO, 5),\
81 SRII(PHASE, DP_DTO, 0),\
82 SRII(PHASE, DP_DTO, 1),\
90 SRII(PHASE, DP_DTO, 0),\
91 SRII(PHASE, DP_DTO, 1),\
[all …]
A Ddce_hwseq.h54 SRII(BLND_CONTROL, BLND, 0), \
55 SRII(BLND_CONTROL, BLND, 1), \
56 SRII(BLND_CONTROL, BLND, 2), \
57 SRII(BLND_CONTROL, BLND, 3), \
58 SRII(BLND_CONTROL, BLND, 4), \
59 SRII(BLND_CONTROL, BLND, 5)
71 SRII(PIXEL_RATE_CNTL, blk, 5)
75 SRII(PIXEL_RATE_CNTL, blk, 1)
91 SRII(PIXEL_RATE_CNTL, blk, 5)
114 SRII(BLND_CONTROL, BLND, 0),\
[all …]
/linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dcn32/
A Ddcn32_mpc.h37 SRII(MPCC_MCM_SHAPER_CONTROL, MPCC_MCM, inst),\
38 SRII(MPCC_MCM_SHAPER_OFFSET_R, MPCC_MCM, inst),\
39 SRII(MPCC_MCM_SHAPER_OFFSET_G, MPCC_MCM, inst),\
40 SRII(MPCC_MCM_SHAPER_OFFSET_B, MPCC_MCM, inst),\
41 SRII(MPCC_MCM_SHAPER_SCALE_R, MPCC_MCM, inst),\
42 SRII(MPCC_MCM_SHAPER_SCALE_G_B, MPCC_MCM, inst),\
44 SRII(MPCC_MCM_SHAPER_LUT_DATA, MPCC_MCM, inst),\
93 SRII(MPCC_MCM_3DLUT_INDEX, MPCC_MCM, inst),\
94 SRII(MPCC_MCM_3DLUT_DATA, MPCC_MCM, inst),\
101 SRII(MPCC_MCM_1DLUT_CONTROL, MPCC_MCM, inst),\
[all …]
A Ddcn32_resource.h790 SRII(CSC_C11_C12_A, MPC_OUT, inst), SRII(CSC_C33_C34_A, MPC_OUT, inst), \
791 SRII(CSC_C11_C12_B, MPC_OUT, inst), SRII(CSC_C33_C34_B, MPC_OUT, inst), \
799 SRII(MPCC_TOP_SEL, MPCC, inst), SRII(MPCC_BOT_SEL, MPCC, inst), \
800 SRII(MPCC_CONTROL, MPCC, inst), SRII(MPCC_STATUS, MPCC, inst), \
801 SRII(MPCC_OPP_ID, MPCC, inst), SRII(MPCC_BG_G_Y, MPCC, inst), \
802 SRII(MPCC_BG_R_CR, MPCC, inst), SRII(MPCC_BG_B_CB, MPCC, inst), \
868 SRII(MPCC_MCM_SHAPER_CONTROL, MPCC_MCM, inst),\
924 SRII(MPCC_MCM_3DLUT_INDEX, MPCC_MCM, inst),\
925 SRII(MPCC_MCM_3DLUT_DATA, MPCC_MCM, inst),\
932 SRII(MPCC_MCM_1DLUT_CONTROL, MPCC_MCM, inst),\
[all …]
A Ddcn32_resource.c151 #define SRII(reg_name, block, id)\ macro
536 SRII(PIXEL_RATE_CNTL, OTG, 0), \
537 SRII(PIXEL_RATE_CNTL, OTG, 1),\
538 SRII(PIXEL_RATE_CNTL, OTG, 2),\
539 SRII(PIXEL_RATE_CNTL, OTG, 3),\
540 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\
541 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\
542 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\
543 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\
/linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dcn20/
A Ddcn20_mpc.h35 SRII(MPCC_TOP_GAIN, MPCC, inst),\
36 SRII(MPCC_BOT_GAIN_INSIDE, MPCC, inst),\
66 SRII(MPCC_MEM_PWR_CTRL, MPCC, inst),\
70 SRII(MPCC_OGAM_MODE, MPCC_OGAM, inst)
74 SRII(CSC_MODE, MPC_OUT, inst),\
75 SRII(CSC_C11_C12_A, MPC_OUT, inst),\
76 SRII(CSC_C33_C34_A, MPC_OUT, inst),\
77 SRII(CSC_C11_C12_B, MPC_OUT, inst),\
78 SRII(CSC_C33_C34_B, MPC_OUT, inst),\
79 SRII(DENORM_CONTROL, MPC_OUT, inst),\
[all …]
/linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dcn30/
A Ddcn30_mpc.h47 SRII(MPCC_TOP_GAIN, MPCC, inst),\
48 SRII(MPCC_BOT_GAIN_INSIDE, MPCC, inst),\
50 SRII(MPCC_MEM_PWR_CTRL, MPCC, inst),\
104 SRII(CSC_MODE, MPC_OUT, inst),\
105 SRII(CSC_C11_C12_A, MPC_OUT, inst),\
106 SRII(CSC_C33_C34_A, MPC_OUT, inst),\
107 SRII(CSC_C11_C12_B, MPC_OUT, inst),\
108 SRII(CSC_C33_C34_B, MPC_OUT, inst),\
109 SRII(DENORM_CONTROL, MPC_OUT, inst),\
119 SRII(SHAPER_CONTROL, MPC_RMU, inst),\
[all …]
/linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dcn10/
A Ddcn10_mpc.h34 SRII(MPCC_TOP_SEL, MPCC, inst),\
35 SRII(MPCC_BOT_SEL, MPCC, inst),\
36 SRII(MPCC_CONTROL, MPCC, inst),\
37 SRII(MPCC_STATUS, MPCC, inst),\
38 SRII(MPCC_OPP_ID, MPCC, inst),\
39 SRII(MPCC_BG_G_Y, MPCC, inst),\
40 SRII(MPCC_BG_R_CR, MPCC, inst),\
41 SRII(MPCC_BG_B_CB, MPCC, inst),\
42 SRII(MPCC_SM_CONTROL, MPCC, inst),\
43 SRII(MPCC_UPDATE_LOCK_SEL, MPCC, inst)
[all …]
A Ddcn10_dwb.h45 #define SRII(reg_name, block, id)\ macro
A Ddcn10_resource.c117 #define SRII(reg_name, block, id)\ macro
/linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dcn316/
A Ddcn316_resource.c165 #define SRII(reg_name, block, id)\ macro
684 SRII(PIXEL_RATE_CNTL, OTG, 0), \
685 SRII(PIXEL_RATE_CNTL, OTG, 1),\
686 SRII(PIXEL_RATE_CNTL, OTG, 2),\
687 SRII(PIXEL_RATE_CNTL, OTG, 3),\
688 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\
689 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\
690 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\
691 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\
/linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dcn314/
A Ddcn314_resource.c175 #define SRII(reg_name, block, id)\ macro
710 SRII(PIXEL_RATE_CNTL, OTG, 0), \
711 SRII(PIXEL_RATE_CNTL, OTG, 1),\
712 SRII(PIXEL_RATE_CNTL, OTG, 2),\
713 SRII(PIXEL_RATE_CNTL, OTG, 3),\
714 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\
715 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\
716 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\
717 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\
/linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dcn315/
A Ddcn315_resource.c174 #define SRII(reg_name, block, id)\ macro
684 SRII(PIXEL_RATE_CNTL, OTG, 0), \
685 SRII(PIXEL_RATE_CNTL, OTG, 1),\
686 SRII(PIXEL_RATE_CNTL, OTG, 2),\
687 SRII(PIXEL_RATE_CNTL, OTG, 3),\
688 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\
689 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\
690 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\
691 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\
/linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dcn321/
A Ddcn321_resource.c154 #define SRII(reg_name, block, id)\ macro
534 SRII(PIXEL_RATE_CNTL, OTG, 0), \
535 SRII(PIXEL_RATE_CNTL, OTG, 1),\
536 SRII(PIXEL_RATE_CNTL, OTG, 2),\
537 SRII(PIXEL_RATE_CNTL, OTG, 3),\
538 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\
539 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\
540 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\
541 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\
/linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dcn31/
A Ddcn31_resource.c142 #define SRII(reg_name, block, id)\ macro
687 SRII(PIXEL_RATE_CNTL, OTG, 0), \
688 SRII(PIXEL_RATE_CNTL, OTG, 1),\
689 SRII(PIXEL_RATE_CNTL, OTG, 2),\
690 SRII(PIXEL_RATE_CNTL, OTG, 3),\
691 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\
692 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\
693 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\
694 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\
A Ddcn31_hpo_dp_link_encoder.h68 SRII(RDPCSTX_PHY_CNTL6, RDPCSTX, id)
/linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dce100/
A Ddce100_resource.c487 #define SRII(reg_name, block, id)\ macro
/linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dce120/
A Ddce120_resource.c772 #define SRII(reg_name, block, id)\ macro
/linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dcn201/
A Ddcn201_resource.c263 #define SRII(reg_name, block, id)\ macro
/linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dce112/
A Ddce112_resource.c517 #define SRII(reg_name, block, id)\ macro
/linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dce60/
A Ddce60_resource.c607 #define SRII(reg_name, block, id)\ macro
/linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dce80/
A Ddce80_resource.c610 #define SRII(reg_name, block, id)\ macro
/linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dce110/
A Ddce110_resource.c539 #define SRII(reg_name, block, id)\ macro
/linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dcn303/
A Ddcn303_resource.c181 #define SRII(reg_name, block, id)\ macro
/linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dcn302/
A Ddcn302_resource.c203 #define SRII(reg_name, block, id)\ macro

Completed in 69 milliseconds

12