SUN9I_CPUS_PLL4_DIV_SET (reference) in projects: linux-6.3-rc2

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/linux-6.3-rc2/drivers/clk/sunxi/
A D	clk-sun9i-cpus.c	`42 #define SUN9I_CPUS_PLL4_DIV_SET(reg, div) ((reg & ~SUN9I_CPUS_PLL4_DIV_MASK) \| \ macro 169 reg = SUN9I_CPUS_PLL4_DIV_SET(reg, pre_div); in sun9i_a80_cpus_clk_set_rate()`

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