1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3  * Microchip KSZ8795 register definitions
4  *
5  * Copyright (c) 2017 Microchip Technology Inc.
6  *	Tristram Ha <Tristram.Ha@microchip.com>
7  */
8 
9 #ifndef __KSZ8795_REG_H
10 #define __KSZ8795_REG_H
11 
12 #define KS_PORT_M			0x1F
13 
14 #define KS_PRIO_M			0x3
15 #define KS_PRIO_S			2
16 
17 #define SW_REVISION_M			0x0E
18 #define SW_REVISION_S			1
19 
20 #define KSZ8863_REG_SW_RESET		0x43
21 
22 #define KSZ8863_GLOBAL_SOFTWARE_RESET	BIT(4)
23 #define KSZ8863_PCS_RESET		BIT(0)
24 
25 #define REG_SW_CTRL_0			0x02
26 
27 #define SW_NEW_BACKOFF			BIT(7)
28 #define SW_GLOBAL_RESET			BIT(6)
29 #define SW_FLUSH_DYN_MAC_TABLE		BIT(5)
30 #define SW_FLUSH_STA_MAC_TABLE		BIT(4)
31 #define SW_LINK_AUTO_AGING		BIT(0)
32 
33 #define REG_SW_CTRL_1			0x03
34 
35 #define SW_HUGE_PACKET			BIT(6)
36 #define SW_TX_FLOW_CTRL_DISABLE		BIT(5)
37 #define SW_RX_FLOW_CTRL_DISABLE		BIT(4)
38 #define SW_CHECK_LENGTH			BIT(3)
39 #define SW_AGING_ENABLE			BIT(2)
40 #define SW_FAST_AGING			BIT(1)
41 #define SW_AGGR_BACKOFF			BIT(0)
42 
43 #define REG_SW_CTRL_2			0x04
44 
45 #define UNICAST_VLAN_BOUNDARY		BIT(7)
46 #define SW_BACK_PRESSURE		BIT(5)
47 #define FAIR_FLOW_CTRL			BIT(4)
48 #define NO_EXC_COLLISION_DROP		BIT(3)
49 #define SW_LEGAL_PACKET_DISABLE		BIT(1)
50 
51 #define KSZ8863_HUGE_PACKET_ENABLE	BIT(2)
52 #define KSZ8863_LEGAL_PACKET_ENABLE	BIT(1)
53 
54 #define REG_SW_CTRL_3			0x05
55  #define WEIGHTED_FAIR_QUEUE_ENABLE	BIT(3)
56 
57 #define SW_VLAN_ENABLE			BIT(7)
58 #define SW_IGMP_SNOOP			BIT(6)
59 #define SW_MIRROR_RX_TX			BIT(0)
60 
61 #define REG_SW_CTRL_4			0x06
62 
63 #define SW_HALF_DUPLEX_FLOW_CTRL	BIT(7)
64 #define SW_HALF_DUPLEX			BIT(6)
65 #define SW_FLOW_CTRL			BIT(5)
66 #define SW_10_MBIT			BIT(4)
67 #define SW_REPLACE_VID			BIT(3)
68 
69 #define REG_SW_CTRL_5			0x07
70 
71 #define REG_SW_CTRL_6			0x08
72 
73 #define SW_MIB_COUNTER_FLUSH		BIT(7)
74 #define SW_MIB_COUNTER_FREEZE		BIT(6)
75 #define SW_MIB_COUNTER_CTRL_ENABLE	KS_PORT_M
76 
77 #define REG_SW_CTRL_9			0x0B
78 
79 #define SPI_CLK_125_MHZ			0x80
80 #define SPI_CLK_62_5_MHZ		0x40
81 #define SPI_CLK_31_25_MHZ		0x00
82 
83 #define SW_LED_MODE_M			0x3
84 #define SW_LED_MODE_S			4
85 #define SW_LED_LINK_ACT_SPEED		0
86 #define SW_LED_LINK_ACT			1
87 #define SW_LED_LINK_ACT_DUPLEX		2
88 #define SW_LED_LINK_DUPLEX		3
89 
90 #define REG_SW_CTRL_10			0x0C
91 
92 #define SW_PASS_PAUSE			BIT(0)
93 
94 #define REG_SW_CTRL_11			0x0D
95 
96 #define REG_POWER_MANAGEMENT_1		0x0E
97 
98 #define SW_PLL_POWER_DOWN		BIT(5)
99 #define SW_POWER_MANAGEMENT_MODE_M	0x3
100 #define SW_POWER_MANAGEMENT_MODE_S	3
101 #define SW_POWER_NORMAL			0
102 #define SW_ENERGY_DETECTION		1
103 #define SW_SOFTWARE_POWER_DOWN		2
104 
105 #define REG_POWER_MANAGEMENT_2		0x0F
106 
107 #define REG_PORT_1_CTRL_0		0x10
108 #define REG_PORT_2_CTRL_0		0x20
109 #define REG_PORT_3_CTRL_0		0x30
110 #define REG_PORT_4_CTRL_0		0x40
111 #define REG_PORT_5_CTRL_0		0x50
112 
113 #define PORT_BROADCAST_STORM		BIT(7)
114 #define PORT_DIFFSERV_ENABLE		BIT(6)
115 #define PORT_802_1P_ENABLE		BIT(5)
116 #define PORT_BASED_PRIO_S		3
117 #define PORT_BASED_PRIO_M		KS_PRIO_M
118 #define PORT_BASED_PRIO_0		0
119 #define PORT_BASED_PRIO_1		1
120 #define PORT_BASED_PRIO_2		2
121 #define PORT_BASED_PRIO_3		3
122 #define PORT_INSERT_TAG			BIT(2)
123 #define PORT_REMOVE_TAG			BIT(1)
124 #define PORT_QUEUE_SPLIT_L		BIT(0)
125 
126 #define REG_PORT_1_CTRL_1		0x11
127 #define REG_PORT_2_CTRL_1		0x21
128 #define REG_PORT_3_CTRL_1		0x31
129 #define REG_PORT_4_CTRL_1		0x41
130 #define REG_PORT_5_CTRL_1		0x51
131 
132 #define PORT_MIRROR_SNIFFER		BIT(7)
133 #define PORT_MIRROR_RX			BIT(6)
134 #define PORT_MIRROR_TX			BIT(5)
135 #define PORT_VLAN_MEMBERSHIP		KS_PORT_M
136 
137 #define REG_PORT_1_CTRL_2		0x12
138 #define REG_PORT_2_CTRL_2		0x22
139 #define REG_PORT_3_CTRL_2		0x32
140 #define REG_PORT_4_CTRL_2		0x42
141 #define REG_PORT_5_CTRL_2		0x52
142 
143 #define PORT_INGRESS_FILTER		BIT(6)
144 #define PORT_DISCARD_NON_VID		BIT(5)
145 #define PORT_FORCE_FLOW_CTRL		BIT(4)
146 #define PORT_BACK_PRESSURE		BIT(3)
147 
148 #define REG_PORT_1_CTRL_3		0x13
149 #define REG_PORT_2_CTRL_3		0x23
150 #define REG_PORT_3_CTRL_3		0x33
151 #define REG_PORT_4_CTRL_3		0x43
152 #define REG_PORT_5_CTRL_3		0x53
153 #define REG_PORT_1_CTRL_4		0x14
154 #define REG_PORT_2_CTRL_4		0x24
155 #define REG_PORT_3_CTRL_4		0x34
156 #define REG_PORT_4_CTRL_4		0x44
157 #define REG_PORT_5_CTRL_4		0x54
158 
159 #define PORT_DEFAULT_VID		0x0001
160 
161 #define REG_PORT_1_CTRL_5		0x15
162 #define REG_PORT_2_CTRL_5		0x25
163 #define REG_PORT_3_CTRL_5		0x35
164 #define REG_PORT_4_CTRL_5		0x45
165 #define REG_PORT_5_CTRL_5		0x55
166 
167 #define PORT_ACL_ENABLE			BIT(2)
168 #define PORT_AUTHEN_MODE		0x3
169 #define PORT_AUTHEN_PASS		0
170 #define PORT_AUTHEN_BLOCK		1
171 #define PORT_AUTHEN_TRAP		2
172 
173 #define REG_PORT_5_CTRL_6		0x56
174 
175 #define PORT_MII_INTERNAL_CLOCK		BIT(7)
176 #define PORT_GMII_MAC_MODE		BIT(2)
177 
178 #define REG_PORT_1_CTRL_7		0x17
179 #define REG_PORT_2_CTRL_7		0x27
180 #define REG_PORT_3_CTRL_7		0x37
181 #define REG_PORT_4_CTRL_7		0x47
182 
183 #define PORT_AUTO_NEG_ASYM_PAUSE	BIT(5)
184 #define PORT_AUTO_NEG_SYM_PAUSE		BIT(4)
185 #define PORT_AUTO_NEG_100BTX_FD		BIT(3)
186 #define PORT_AUTO_NEG_100BTX		BIT(2)
187 #define PORT_AUTO_NEG_10BT_FD		BIT(1)
188 #define PORT_AUTO_NEG_10BT		BIT(0)
189 
190 #define REG_PORT_1_STATUS_0		0x18
191 #define REG_PORT_2_STATUS_0		0x28
192 #define REG_PORT_3_STATUS_0		0x38
193 #define REG_PORT_4_STATUS_0		0x48
194 
195 /* For KSZ8765. */
196 #define PORT_REMOTE_ASYM_PAUSE		BIT(5)
197 #define PORT_REMOTE_SYM_PAUSE		BIT(4)
198 #define PORT_REMOTE_100BTX_FD		BIT(3)
199 #define PORT_REMOTE_100BTX		BIT(2)
200 #define PORT_REMOTE_10BT_FD		BIT(1)
201 #define PORT_REMOTE_10BT		BIT(0)
202 
203 #define REG_PORT_1_STATUS_1		0x19
204 #define REG_PORT_2_STATUS_1		0x29
205 #define REG_PORT_3_STATUS_1		0x39
206 #define REG_PORT_4_STATUS_1		0x49
207 
208 #define PORT_HP_MDIX			BIT(7)
209 #define PORT_REVERSED_POLARITY		BIT(5)
210 #define PORT_TX_FLOW_CTRL		BIT(4)
211 #define PORT_RX_FLOW_CTRL		BIT(3)
212 #define PORT_STAT_SPEED_100MBIT		BIT(2)
213 #define PORT_STAT_FULL_DUPLEX		BIT(1)
214 
215 #define PORT_REMOTE_FAULT		BIT(0)
216 
217 #define REG_PORT_1_LINK_MD_CTRL		0x1A
218 #define REG_PORT_2_LINK_MD_CTRL		0x2A
219 #define REG_PORT_3_LINK_MD_CTRL		0x3A
220 #define REG_PORT_4_LINK_MD_CTRL		0x4A
221 
222 #define PORT_CABLE_10M_SHORT		BIT(7)
223 #define PORT_CABLE_DIAG_RESULT_M	GENMASK(6, 5)
224 #define PORT_CABLE_DIAG_RESULT_S	5
225 #define PORT_CABLE_STAT_NORMAL		0
226 #define PORT_CABLE_STAT_OPEN		1
227 #define PORT_CABLE_STAT_SHORT		2
228 #define PORT_CABLE_STAT_FAILED		3
229 #define PORT_START_CABLE_DIAG		BIT(4)
230 #define PORT_FORCE_LINK			BIT(3)
231 #define PORT_POWER_SAVING		BIT(2)
232 #define PORT_PHY_REMOTE_LOOPBACK	BIT(1)
233 #define PORT_CABLE_FAULT_COUNTER_H	0x01
234 
235 #define REG_PORT_1_LINK_MD_RESULT	0x1B
236 #define REG_PORT_2_LINK_MD_RESULT	0x2B
237 #define REG_PORT_3_LINK_MD_RESULT	0x3B
238 #define REG_PORT_4_LINK_MD_RESULT	0x4B
239 
240 #define PORT_CABLE_FAULT_COUNTER_L	0xFF
241 #define PORT_CABLE_FAULT_COUNTER	0x1FF
242 
243 #define REG_PORT_1_CTRL_9		0x1C
244 #define REG_PORT_2_CTRL_9		0x2C
245 #define REG_PORT_3_CTRL_9		0x3C
246 #define REG_PORT_4_CTRL_9		0x4C
247 
248 #define PORT_AUTO_NEG_ENABLE		BIT(7)
249 #define PORT_AUTO_NEG_DISABLE		BIT(7)
250 #define PORT_FORCE_100_MBIT		BIT(6)
251 #define PORT_FORCE_FULL_DUPLEX		BIT(5)
252 
253 #define REG_PORT_1_CTRL_10		0x1D
254 #define REG_PORT_2_CTRL_10		0x2D
255 #define REG_PORT_3_CTRL_10		0x3D
256 #define REG_PORT_4_CTRL_10		0x4D
257 
258 #define PORT_LED_OFF			BIT(7)
259 #define PORT_TX_DISABLE			BIT(6)
260 #define PORT_AUTO_NEG_RESTART		BIT(5)
261 #define PORT_POWER_DOWN			BIT(3)
262 #define PORT_AUTO_MDIX_DISABLE		BIT(2)
263 #define PORT_FORCE_MDIX			BIT(1)
264 #define PORT_MAC_LOOPBACK		BIT(0)
265 
266 #define REG_PORT_1_STATUS_2		0x1E
267 #define REG_PORT_2_STATUS_2		0x2E
268 #define REG_PORT_3_STATUS_2		0x3E
269 #define REG_PORT_4_STATUS_2		0x4E
270 
271 #define PORT_MDIX_STATUS		BIT(7)
272 #define PORT_AUTO_NEG_COMPLETE		BIT(6)
273 #define PORT_STAT_LINK_GOOD		BIT(5)
274 
275 #define REG_PORT_1_STATUS_3		0x1F
276 #define REG_PORT_2_STATUS_3		0x2F
277 #define REG_PORT_3_STATUS_3		0x3F
278 #define REG_PORT_4_STATUS_3		0x4F
279 
280 #define PORT_PHY_LOOPBACK		BIT(7)
281 #define PORT_PHY_ISOLATE		BIT(5)
282 #define PORT_PHY_SOFT_RESET		BIT(4)
283 #define PORT_PHY_FORCE_LINK		BIT(3)
284 #define PORT_PHY_MODE_M			0x7
285 #define PHY_MODE_IN_AUTO_NEG		1
286 #define PHY_MODE_10BT_HALF		2
287 #define PHY_MODE_100BT_HALF		3
288 #define PHY_MODE_10BT_FULL		5
289 #define PHY_MODE_100BT_FULL		6
290 #define PHY_MODE_ISOLDATE		7
291 
292 #define REG_PORT_CTRL_0			0x00
293 #define REG_PORT_CTRL_1			0x01
294 #define REG_PORT_CTRL_2			0x02
295 #define REG_PORT_CTRL_VID		0x03
296 
297 #define REG_PORT_CTRL_5			0x05
298 
299 #define REG_PORT_STATUS_1		0x09
300 #define REG_PORT_LINK_MD_CTRL		0x0A
301 #define REG_PORT_LINK_MD_RESULT		0x0B
302 #define REG_PORT_CTRL_9			0x0C
303 #define REG_PORT_CTRL_10		0x0D
304 #define REG_PORT_STATUS_3		0x0F
305 
306 #define REG_PORT_CTRL_12		0xA0
307 #define REG_PORT_CTRL_13		0xA1
308 #define REG_PORT_RATE_CTRL_3		0xA2
309 #define REG_PORT_RATE_CTRL_2		0xA3
310 #define REG_PORT_RATE_CTRL_1		0xA4
311 #define REG_PORT_RATE_CTRL_0		0xA5
312 #define REG_PORT_RATE_LIMIT		0xA6
313 #define REG_PORT_IN_RATE_0		0xA7
314 #define REG_PORT_IN_RATE_1		0xA8
315 #define REG_PORT_IN_RATE_2		0xA9
316 #define REG_PORT_IN_RATE_3		0xAA
317 #define REG_PORT_OUT_RATE_0		0xAB
318 #define REG_PORT_OUT_RATE_1		0xAC
319 #define REG_PORT_OUT_RATE_2		0xAD
320 #define REG_PORT_OUT_RATE_3		0xAE
321 
322 #define PORT_CTRL_ADDR(port, addr)		\
323 	((addr) + REG_PORT_1_CTRL_0 + (port) *	\
324 		(REG_PORT_2_CTRL_0 - REG_PORT_1_CTRL_0))
325 
326 #define REG_SW_MAC_ADDR_0		0x68
327 #define REG_SW_MAC_ADDR_1		0x69
328 #define REG_SW_MAC_ADDR_2		0x6A
329 #define REG_SW_MAC_ADDR_3		0x6B
330 #define REG_SW_MAC_ADDR_4		0x6C
331 #define REG_SW_MAC_ADDR_5		0x6D
332 
333 #define TABLE_EXT_SELECT_S		5
334 #define TABLE_EEE_V			1
335 #define TABLE_ACL_V			2
336 #define TABLE_PME_V			4
337 #define TABLE_LINK_MD_V			5
338 #define TABLE_EEE			(TABLE_EEE_V << TABLE_EXT_SELECT_S)
339 #define TABLE_ACL			(TABLE_ACL_V << TABLE_EXT_SELECT_S)
340 #define TABLE_PME			(TABLE_PME_V << TABLE_EXT_SELECT_S)
341 #define TABLE_LINK_MD			(TABLE_LINK_MD << TABLE_EXT_SELECT_S)
342 #define TABLE_READ			BIT(4)
343 #define TABLE_SELECT_S			2
344 #define TABLE_STATIC_MAC_V		0
345 #define TABLE_VLAN_V			1
346 #define TABLE_DYNAMIC_MAC_V		2
347 #define TABLE_MIB_V			3
348 #define TABLE_STATIC_MAC		(TABLE_STATIC_MAC_V << TABLE_SELECT_S)
349 #define TABLE_VLAN			(TABLE_VLAN_V << TABLE_SELECT_S)
350 #define TABLE_DYNAMIC_MAC		(TABLE_DYNAMIC_MAC_V << TABLE_SELECT_S)
351 #define TABLE_MIB			(TABLE_MIB_V << TABLE_SELECT_S)
352 
353 #define REG_IND_CTRL_1			0x6F
354 
355 #define TABLE_ENTRY_MASK		0x03FF
356 #define TABLE_EXT_ENTRY_MASK		0x0FFF
357 
358 #define REG_IND_DATA_5			0x73
359 #define REG_IND_DATA_2			0x76
360 #define REG_IND_DATA_1			0x77
361 #define REG_IND_DATA_0			0x78
362 
363 #define REG_IND_DATA_PME_EEE_ACL	0xA0
364 
365 #define REG_INT_STATUS			0x7C
366 #define REG_INT_ENABLE			0x7D
367 
368 #define INT_PME				BIT(4)
369 
370 #define REG_ACL_INT_STATUS		0x7E
371 #define REG_ACL_INT_ENABLE		0x7F
372 
373 #define INT_PORT_5			BIT(4)
374 #define INT_PORT_4			BIT(3)
375 #define INT_PORT_3			BIT(2)
376 #define INT_PORT_2			BIT(1)
377 #define INT_PORT_1			BIT(0)
378 
379 #define INT_PORT_ALL			\
380 	(INT_PORT_5 | INT_PORT_4 | INT_PORT_3 | INT_PORT_2 | INT_PORT_1)
381 
382 #define REG_SW_CTRL_12			0x80
383 #define REG_SW_CTRL_13			0x81
384 
385 #define SWITCH_802_1P_MASK		3
386 #define SWITCH_802_1P_BASE		3
387 #define SWITCH_802_1P_SHIFT		2
388 
389 #define SW_802_1P_MAP_M			KS_PRIO_M
390 #define SW_802_1P_MAP_S			KS_PRIO_S
391 
392 #define REG_SWITCH_CTRL_14		0x82
393 
394 #define SW_PRIO_MAPPING_M		KS_PRIO_M
395 #define SW_PRIO_MAPPING_S		6
396 #define SW_PRIO_MAP_3_HI		0
397 #define SW_PRIO_MAP_2_HI		2
398 #define SW_PRIO_MAP_0_LO		3
399 
400 #define REG_SW_CTRL_15			0x83
401 #define REG_SW_CTRL_16			0x84
402 #define REG_SW_CTRL_17			0x85
403 #define REG_SW_CTRL_18			0x86
404 
405 #define SW_SELF_ADDR_FILTER_ENABLE	BIT(6)
406 
407 #define REG_SW_UNK_UCAST_CTRL		0x83
408 #define REG_SW_UNK_MCAST_CTRL		0x84
409 #define REG_SW_UNK_VID_CTRL		0x85
410 #define REG_SW_UNK_IP_MCAST_CTRL	0x86
411 
412 #define SW_UNK_FWD_ENABLE		BIT(5)
413 #define SW_UNK_FWD_MAP			KS_PORT_M
414 
415 #define REG_SW_CTRL_19			0x87
416 
417 #define SW_IN_RATE_LIMIT_PERIOD_M	0x3
418 #define SW_IN_RATE_LIMIT_PERIOD_S	4
419 #define SW_IN_RATE_LIMIT_16_MS		0
420 #define SW_IN_RATE_LIMIT_64_MS		1
421 #define SW_IN_RATE_LIMIT_256_MS		2
422 #define SW_OUT_RATE_LIMIT_QUEUE_BASED	BIT(3)
423 #define SW_INS_TAG_ENABLE		BIT(2)
424 
425 #define REG_TOS_PRIO_CTRL_0		0x90
426 #define REG_TOS_PRIO_CTRL_1		0x91
427 #define REG_TOS_PRIO_CTRL_2		0x92
428 #define REG_TOS_PRIO_CTRL_3		0x93
429 #define REG_TOS_PRIO_CTRL_4		0x94
430 #define REG_TOS_PRIO_CTRL_5		0x95
431 #define REG_TOS_PRIO_CTRL_6		0x96
432 #define REG_TOS_PRIO_CTRL_7		0x97
433 #define REG_TOS_PRIO_CTRL_8		0x98
434 #define REG_TOS_PRIO_CTRL_9		0x99
435 #define REG_TOS_PRIO_CTRL_10		0x9A
436 #define REG_TOS_PRIO_CTRL_11		0x9B
437 #define REG_TOS_PRIO_CTRL_12		0x9C
438 #define REG_TOS_PRIO_CTRL_13		0x9D
439 #define REG_TOS_PRIO_CTRL_14		0x9E
440 #define REG_TOS_PRIO_CTRL_15		0x9F
441 
442 #define TOS_PRIO_M			KS_PRIO_M
443 #define TOS_PRIO_S			KS_PRIO_S
444 
445 #define REG_SW_CTRL_20			0xA3
446 
447 #define SW_GMII_DRIVE_STRENGTH_S	4
448 #define SW_DRIVE_STRENGTH_M		0x7
449 #define SW_DRIVE_STRENGTH_2MA		0
450 #define SW_DRIVE_STRENGTH_4MA		1
451 #define SW_DRIVE_STRENGTH_8MA		2
452 #define SW_DRIVE_STRENGTH_12MA		3
453 #define SW_DRIVE_STRENGTH_16MA		4
454 #define SW_DRIVE_STRENGTH_20MA		5
455 #define SW_DRIVE_STRENGTH_24MA		6
456 #define SW_DRIVE_STRENGTH_28MA		7
457 #define SW_MII_DRIVE_STRENGTH_S		0
458 
459 #define REG_SW_CTRL_21			0xA4
460 
461 #define SW_IPV6_MLD_OPTION		BIT(3)
462 #define SW_IPV6_MLD_SNOOP		BIT(2)
463 
464 #define REG_PORT_1_CTRL_12		0xB0
465 #define REG_PORT_2_CTRL_12		0xC0
466 #define REG_PORT_3_CTRL_12		0xD0
467 #define REG_PORT_4_CTRL_12		0xE0
468 #define REG_PORT_5_CTRL_12		0xF0
469 
470 #define PORT_PASS_ALL			BIT(6)
471 #define PORT_INS_TAG_FOR_PORT_5_S	3
472 #define PORT_INS_TAG_FOR_PORT_5		BIT(3)
473 #define PORT_INS_TAG_FOR_PORT_4		BIT(2)
474 #define PORT_INS_TAG_FOR_PORT_3		BIT(1)
475 #define PORT_INS_TAG_FOR_PORT_2		BIT(0)
476 
477 #define REG_PORT_1_CTRL_13		0xB1
478 #define REG_PORT_2_CTRL_13		0xC1
479 #define REG_PORT_3_CTRL_13		0xD1
480 #define REG_PORT_4_CTRL_13		0xE1
481 #define REG_PORT_5_CTRL_13		0xF1
482 
483 #define PORT_QUEUE_SPLIT_H		BIT(1)
484 #define PORT_QUEUE_SPLIT_1		0
485 #define PORT_QUEUE_SPLIT_2		1
486 #define PORT_QUEUE_SPLIT_4		2
487 #define PORT_DROP_TAG			BIT(0)
488 
489 #define REG_PORT_1_CTRL_14		0xB2
490 #define REG_PORT_2_CTRL_14		0xC2
491 #define REG_PORT_3_CTRL_14		0xD2
492 #define REG_PORT_4_CTRL_14		0xE2
493 #define REG_PORT_5_CTRL_14		0xF2
494 #define REG_PORT_1_CTRL_15		0xB3
495 #define REG_PORT_2_CTRL_15		0xC3
496 #define REG_PORT_3_CTRL_15		0xD3
497 #define REG_PORT_4_CTRL_15		0xE3
498 #define REG_PORT_5_CTRL_15		0xF3
499 #define REG_PORT_1_CTRL_16		0xB4
500 #define REG_PORT_2_CTRL_16		0xC4
501 #define REG_PORT_3_CTRL_16		0xD4
502 #define REG_PORT_4_CTRL_16		0xE4
503 #define REG_PORT_5_CTRL_16		0xF4
504 #define REG_PORT_1_CTRL_17		0xB5
505 #define REG_PORT_2_CTRL_17		0xC5
506 #define REG_PORT_3_CTRL_17		0xD5
507 #define REG_PORT_4_CTRL_17		0xE5
508 #define REG_PORT_5_CTRL_17		0xF5
509 
510 #define REG_PORT_1_RATE_CTRL_3		0xB2
511 #define REG_PORT_1_RATE_CTRL_2		0xB3
512 #define REG_PORT_1_RATE_CTRL_1		0xB4
513 #define REG_PORT_1_RATE_CTRL_0		0xB5
514 #define REG_PORT_2_RATE_CTRL_3		0xC2
515 #define REG_PORT_2_RATE_CTRL_2		0xC3
516 #define REG_PORT_2_RATE_CTRL_1		0xC4
517 #define REG_PORT_2_RATE_CTRL_0		0xC5
518 #define REG_PORT_3_RATE_CTRL_3		0xD2
519 #define REG_PORT_3_RATE_CTRL_2		0xD3
520 #define REG_PORT_3_RATE_CTRL_1		0xD4
521 #define REG_PORT_3_RATE_CTRL_0		0xD5
522 #define REG_PORT_4_RATE_CTRL_3		0xE2
523 #define REG_PORT_4_RATE_CTRL_2		0xE3
524 #define REG_PORT_4_RATE_CTRL_1		0xE4
525 #define REG_PORT_4_RATE_CTRL_0		0xE5
526 #define REG_PORT_5_RATE_CTRL_3		0xF2
527 #define REG_PORT_5_RATE_CTRL_2		0xF3
528 #define REG_PORT_5_RATE_CTRL_1		0xF4
529 #define REG_PORT_5_RATE_CTRL_0		0xF5
530 
531 #define RATE_CTRL_ENABLE		BIT(7)
532 #define RATE_RATIO_M			(BIT(7) - 1)
533 
534 #define PORT_OUT_RATE_ENABLE		BIT(7)
535 
536 #define REG_PORT_1_RATE_LIMIT		0xB6
537 #define REG_PORT_2_RATE_LIMIT		0xC6
538 #define REG_PORT_3_RATE_LIMIT		0xD6
539 #define REG_PORT_4_RATE_LIMIT		0xE6
540 #define REG_PORT_5_RATE_LIMIT		0xF6
541 
542 #define PORT_IN_PORT_BASED_S		6
543 #define PORT_RATE_PACKET_BASED_S	5
544 #define PORT_IN_FLOW_CTRL_S		4
545 #define PORT_IN_LIMIT_MODE_M		0x3
546 #define PORT_IN_LIMIT_MODE_S		2
547 #define PORT_COUNT_IFG_S		1
548 #define PORT_COUNT_PREAMBLE_S		0
549 #define PORT_IN_PORT_BASED		BIT(PORT_IN_PORT_BASED_S)
550 #define PORT_RATE_PACKET_BASED		BIT(PORT_RATE_PACKET_BASED_S)
551 #define PORT_IN_FLOW_CTRL		BIT(PORT_IN_FLOW_CTRL_S)
552 #define PORT_IN_ALL			0
553 #define PORT_IN_UNICAST			1
554 #define PORT_IN_MULTICAST		2
555 #define PORT_IN_BROADCAST		3
556 #define PORT_COUNT_IFG			BIT(PORT_COUNT_IFG_S)
557 #define PORT_COUNT_PREAMBLE		BIT(PORT_COUNT_PREAMBLE_S)
558 
559 #define REG_PORT_1_IN_RATE_0		0xB7
560 #define REG_PORT_2_IN_RATE_0		0xC7
561 #define REG_PORT_3_IN_RATE_0		0xD7
562 #define REG_PORT_4_IN_RATE_0		0xE7
563 #define REG_PORT_5_IN_RATE_0		0xF7
564 #define REG_PORT_1_IN_RATE_1		0xB8
565 #define REG_PORT_2_IN_RATE_1		0xC8
566 #define REG_PORT_3_IN_RATE_1		0xD8
567 #define REG_PORT_4_IN_RATE_1		0xE8
568 #define REG_PORT_5_IN_RATE_1		0xF8
569 #define REG_PORT_1_IN_RATE_2		0xB9
570 #define REG_PORT_2_IN_RATE_2		0xC9
571 #define REG_PORT_3_IN_RATE_2		0xD9
572 #define REG_PORT_4_IN_RATE_2		0xE9
573 #define REG_PORT_5_IN_RATE_2		0xF9
574 #define REG_PORT_1_IN_RATE_3		0xBA
575 #define REG_PORT_2_IN_RATE_3		0xCA
576 #define REG_PORT_3_IN_RATE_3		0xDA
577 #define REG_PORT_4_IN_RATE_3		0xEA
578 #define REG_PORT_5_IN_RATE_3		0xFA
579 
580 #define PORT_IN_RATE_ENABLE		BIT(7)
581 #define PORT_RATE_LIMIT_M		(BIT(7) - 1)
582 
583 #define REG_PORT_1_OUT_RATE_0		0xBB
584 #define REG_PORT_2_OUT_RATE_0		0xCB
585 #define REG_PORT_3_OUT_RATE_0		0xDB
586 #define REG_PORT_4_OUT_RATE_0		0xEB
587 #define REG_PORT_5_OUT_RATE_0		0xFB
588 #define REG_PORT_1_OUT_RATE_1		0xBC
589 #define REG_PORT_2_OUT_RATE_1		0xCC
590 #define REG_PORT_3_OUT_RATE_1		0xDC
591 #define REG_PORT_4_OUT_RATE_1		0xEC
592 #define REG_PORT_5_OUT_RATE_1		0xFC
593 #define REG_PORT_1_OUT_RATE_2		0xBD
594 #define REG_PORT_2_OUT_RATE_2		0xCD
595 #define REG_PORT_3_OUT_RATE_2		0xDD
596 #define REG_PORT_4_OUT_RATE_2		0xED
597 #define REG_PORT_5_OUT_RATE_2		0xFD
598 #define REG_PORT_1_OUT_RATE_3		0xBE
599 #define REG_PORT_2_OUT_RATE_3		0xCE
600 #define REG_PORT_3_OUT_RATE_3		0xDE
601 #define REG_PORT_4_OUT_RATE_3		0xEE
602 #define REG_PORT_5_OUT_RATE_3		0xFE
603 
604 /* 88x3 specific */
605 
606 #define REG_SW_INSERT_SRC_PVID		0xC2
607 
608 /* PME */
609 
610 #define SW_PME_OUTPUT_ENABLE		BIT(1)
611 #define SW_PME_ACTIVE_HIGH		BIT(0)
612 
613 #define PORT_MAGIC_PACKET_DETECT	BIT(2)
614 #define PORT_LINK_UP_DETECT		BIT(1)
615 #define PORT_ENERGY_DETECT		BIT(0)
616 
617 /* ACL */
618 
619 #define ACL_FIRST_RULE_M		0xF
620 
621 #define ACL_MODE_M			0x3
622 #define ACL_MODE_S			4
623 #define ACL_MODE_DISABLE		0
624 #define ACL_MODE_LAYER_2		1
625 #define ACL_MODE_LAYER_3		2
626 #define ACL_MODE_LAYER_4		3
627 #define ACL_ENABLE_M			0x3
628 #define ACL_ENABLE_S			2
629 #define ACL_ENABLE_2_COUNT		0
630 #define ACL_ENABLE_2_TYPE		1
631 #define ACL_ENABLE_2_MAC		2
632 #define ACL_ENABLE_2_BOTH		3
633 #define ACL_ENABLE_3_IP			1
634 #define ACL_ENABLE_3_SRC_DST_COMP	2
635 #define ACL_ENABLE_4_PROTOCOL		0
636 #define ACL_ENABLE_4_TCP_PORT_COMP	1
637 #define ACL_ENABLE_4_UDP_PORT_COMP	2
638 #define ACL_ENABLE_4_TCP_SEQN_COMP	3
639 #define ACL_SRC				BIT(1)
640 #define ACL_EQUAL			BIT(0)
641 
642 #define ACL_MAX_PORT			0xFFFF
643 
644 #define ACL_MIN_PORT			0xFFFF
645 #define ACL_IP_ADDR			0xFFFFFFFF
646 #define ACL_TCP_SEQNUM			0xFFFFFFFF
647 
648 #define ACL_RESERVED			0xF8
649 #define ACL_PORT_MODE_M			0x3
650 #define ACL_PORT_MODE_S			1
651 #define ACL_PORT_MODE_DISABLE		0
652 #define ACL_PORT_MODE_EITHER		1
653 #define ACL_PORT_MODE_IN_RANGE		2
654 #define ACL_PORT_MODE_OUT_OF_RANGE	3
655 
656 #define ACL_TCP_FLAG_ENABLE		BIT(0)
657 
658 #define ACL_TCP_FLAG_M			0xFF
659 
660 #define ACL_TCP_FLAG			0xFF
661 #define ACL_ETH_TYPE			0xFFFF
662 #define ACL_IP_M			0xFFFFFFFF
663 
664 #define ACL_PRIO_MODE_M			0x3
665 #define ACL_PRIO_MODE_S			6
666 #define ACL_PRIO_MODE_DISABLE		0
667 #define ACL_PRIO_MODE_HIGHER		1
668 #define ACL_PRIO_MODE_LOWER		2
669 #define ACL_PRIO_MODE_REPLACE		3
670 #define ACL_PRIO_M			0x7
671 #define ACL_PRIO_S			3
672 #define ACL_VLAN_PRIO_REPLACE		BIT(2)
673 #define ACL_VLAN_PRIO_M			0x7
674 #define ACL_VLAN_PRIO_HI_M		0x3
675 
676 #define ACL_VLAN_PRIO_LO_M		0x8
677 #define ACL_VLAN_PRIO_S			7
678 #define ACL_MAP_MODE_M			0x3
679 #define ACL_MAP_MODE_S			5
680 #define ACL_MAP_MODE_DISABLE		0
681 #define ACL_MAP_MODE_OR			1
682 #define ACL_MAP_MODE_AND		2
683 #define ACL_MAP_MODE_REPLACE		3
684 #define ACL_MAP_PORT_M			0x1F
685 
686 #define ACL_CNT_M			(BIT(11) - 1)
687 #define ACL_CNT_S			5
688 #define ACL_MSEC_UNIT			BIT(4)
689 #define ACL_INTR_MODE			BIT(3)
690 
691 #define REG_PORT_ACL_BYTE_EN_MSB	0x10
692 
693 #define ACL_BYTE_EN_MSB_M		0x3F
694 
695 #define REG_PORT_ACL_BYTE_EN_LSB	0x11
696 
697 #define ACL_ACTION_START		0xA
698 #define ACL_ACTION_LEN			2
699 #define ACL_INTR_CNT_START		0xB
700 #define ACL_RULESET_START		0xC
701 #define ACL_RULESET_LEN			2
702 #define ACL_TABLE_LEN			14
703 
704 #define ACL_ACTION_ENABLE		0x000C
705 #define ACL_MATCH_ENABLE		0x1FF0
706 #define ACL_RULESET_ENABLE		0x2003
707 #define ACL_BYTE_ENABLE			((ACL_BYTE_EN_MSB_M << 8) | 0xFF)
708 #define ACL_MODE_ENABLE			(0x10 << 8)
709 
710 #define REG_PORT_ACL_CTRL_0		0x12
711 
712 #define PORT_ACL_WRITE_DONE		BIT(6)
713 #define PORT_ACL_READ_DONE		BIT(5)
714 #define PORT_ACL_WRITE			BIT(4)
715 #define PORT_ACL_INDEX_M		0xF
716 
717 #define REG_PORT_ACL_CTRL_1		0x13
718 
719 #define PORT_ACL_FORCE_DLR_MISS		BIT(0)
720 
721 #define KSZ8795_ID_HI			0x0022
722 #define KSZ8795_ID_LO			0x1550
723 #define KSZ8863_ID_LO			0x1430
724 
725 #define KSZ8795_SW_ID			0x8795
726 
727 #define PHY_REG_LINK_MD			0x1D
728 
729 #define PHY_START_CABLE_DIAG		BIT(15)
730 #define PHY_CABLE_DIAG_RESULT_M		GENMASK(14, 13)
731 #define PHY_CABLE_DIAG_RESULT		0x6000
732 #define PHY_CABLE_STAT_NORMAL		0x0000
733 #define PHY_CABLE_STAT_OPEN		0x2000
734 #define PHY_CABLE_STAT_SHORT		0x4000
735 #define PHY_CABLE_STAT_FAILED		0x6000
736 #define PHY_CABLE_10M_SHORT		BIT(12)
737 #define PHY_CABLE_FAULT_COUNTER_M	GENMASK(8, 0)
738 
739 #define PHY_REG_PHY_CTRL		0x1F
740 
741 #define PHY_MODE_M			0x7
742 #define PHY_MODE_S			8
743 #define PHY_STAT_REVERSED_POLARITY	BIT(5)
744 #define PHY_STAT_MDIX			BIT(4)
745 #define PHY_FORCE_LINK			BIT(3)
746 #define PHY_POWER_SAVING_ENABLE		BIT(2)
747 #define PHY_REMOTE_LOOPBACK		BIT(1)
748 
749 /* Chip resource */
750 
751 #define PRIO_QUEUES			4
752 
753 #define KS_PRIO_IN_REG			4
754 
755 #define MIB_COUNTER_NUM		0x20
756 
757 /* Common names used by other drivers */
758 
759 #define P_BCAST_STORM_CTRL		REG_PORT_CTRL_0
760 #define P_PRIO_CTRL			REG_PORT_CTRL_0
761 #define P_TAG_CTRL			REG_PORT_CTRL_0
762 #define P_MIRROR_CTRL			REG_PORT_CTRL_1
763 #define P_802_1P_CTRL			REG_PORT_CTRL_2
764 #define P_PASS_ALL_CTRL			REG_PORT_CTRL_12
765 #define P_INS_SRC_PVID_CTRL		REG_PORT_CTRL_12
766 #define P_DROP_TAG_CTRL			REG_PORT_CTRL_13
767 #define P_RATE_LIMIT_CTRL		REG_PORT_RATE_LIMIT
768 
769 #define S_UNKNOWN_DA_CTRL		REG_SWITCH_CTRL_12
770 #define S_FORWARD_INVALID_VID_CTRL	REG_FORWARD_INVALID_VID
771 
772 #define S_FLUSH_TABLE_CTRL		REG_SW_CTRL_0
773 #define S_LINK_AGING_CTRL		REG_SW_CTRL_0
774 #define S_HUGE_PACKET_CTRL		REG_SW_CTRL_1
775 #define S_MIRROR_CTRL			REG_SW_CTRL_3
776 #define S_REPLACE_VID_CTRL		REG_SW_CTRL_4
777 #define S_PASS_PAUSE_CTRL		REG_SW_CTRL_10
778 #define S_802_1P_PRIO_CTRL		REG_SW_CTRL_12
779 #define S_TOS_PRIO_CTRL			REG_TOS_PRIO_CTRL_0
780 #define S_IPV6_MLD_CTRL			REG_SW_CTRL_21
781 
782 #define IND_ACC_TABLE(table)		((table) << 8)
783 
784 /* */
785 #define REG_IND_EEE_GLOB2_LO		0x34
786 #define REG_IND_EEE_GLOB2_HI		0x35
787 
788 /**
789  * MIB_COUNTER_VALUE			00-00000000-3FFFFFFF
790  * MIB_TOTAL_BYTES			00-0000000F-FFFFFFFF
791  * MIB_PACKET_DROPPED			00-00000000-0000FFFF
792  * MIB_COUNTER_VALID			00-00000020-00000000
793  * MIB_COUNTER_OVERFLOW			00-00000040-00000000
794  */
795 
796 #define MIB_COUNTER_VALUE		0x3FFFFFFF
797 
798 #define KSZ8795_MIB_TOTAL_RX_0		0x100
799 #define KSZ8795_MIB_TOTAL_TX_0		0x101
800 #define KSZ8795_MIB_TOTAL_RX_1		0x104
801 #define KSZ8795_MIB_TOTAL_TX_1		0x105
802 
803 #define KSZ8863_MIB_PACKET_DROPPED_TX_0 0x100
804 #define KSZ8863_MIB_PACKET_DROPPED_RX_0 0x105
805 
806 #define MIB_PACKET_DROPPED		0x0000FFFF
807 
808 #define MIB_TOTAL_BYTES_H		0x0000000F
809 
810 #define TAIL_TAG_OVERRIDE		BIT(6)
811 #define TAIL_TAG_LOOKUP			BIT(7)
812 
813 #define FID_ENTRIES			128
814 
815 #endif
816