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Searched refs:SYSCLK (Results 1 – 10 of 10) sorted by relevance

/linux-6.3-rc2/drivers/clk/davinci/
A Dpll-da850.c49 SYSCLK(1, pll0_sysclk1, pll0_pllen, 5, SYSCLK_FIXED_DIV);
50 SYSCLK(2, pll0_sysclk2, pll0_pllen, 5, SYSCLK_FIXED_DIV);
51 SYSCLK(3, pll0_sysclk3, pll0_pllen, 5, 0);
52 SYSCLK(4, pll0_sysclk4, pll0_pllen, 5, SYSCLK_FIXED_DIV);
53 SYSCLK(5, pll0_sysclk5, pll0_pllen, 5, 0);
54 SYSCLK(6, pll0_sysclk6, pll0_pllen, 5, SYSCLK_ARM_RATE | SYSCLK_FIXED_DIV);
55 SYSCLK(7, pll0_sysclk7, pll0_pllen, 5, 0);
172 SYSCLK(1, pll1_sysclk1, pll1_pllen, 5, SYSCLK_ALWAYS_ENABLED);
173 SYSCLK(2, pll1_sysclk2, pll1_pllen, 5, 0);
174 SYSCLK(3, pll1_sysclk3, pll1_pllen, 5, 0);
A Dpll-da830.c33 SYSCLK(2, pll0_sysclk2, pll0_pllen, 5, SYSCLK_FIXED_DIV);
34 SYSCLK(3, pll0_sysclk3, pll0_pllen, 5, 0);
35 SYSCLK(4, pll0_sysclk4, pll0_pllen, 5, SYSCLK_FIXED_DIV);
36 SYSCLK(5, pll0_sysclk5, pll0_pllen, 5, 0);
37 SYSCLK(6, pll0_sysclk6, pll0_pllen, 5, SYSCLK_FIXED_DIV);
38 SYSCLK(7, pll0_sysclk7, pll0_pllen, 5, 0);
A Dpll.h70 #define SYSCLK(i, n, p, w, f) \ macro
/linux-6.3-rc2/Documentation/devicetree/bindings/clock/
A Dqoriq-clock.txt4 SYSCLK signal. The SYSCLK input (frequency) is multiplied using
64 - clock-frequency: Input system clock frequency (SYSCLK)
/linux-6.3-rc2/Documentation/sound/soc/
A Dplatform.rst62 4. SYSCLK configuration
A Dclocking.rst13 or SYSCLK). This audio master clock can be derived from a number of sources
A Ddai.rst31 (SYSCLK). LRCLK is the same as the sample rate. A few devices support separate
/linux-6.3-rc2/arch/arm/boot/dts/
A Dintegratorap.dts119 * SYSCLK clocks PCIv3 bridge, system controller and the
/linux-6.3-rc2/drivers/pinctrl/tegra/
A Dpinctrl-tegra114.c1747 …PINGROUP(sys_clk_req_pz5, SYSCLK, RSVD2, RSVD3, RSVD4, 0x3320, N, N…
A Dpinctrl-tegra30.c2379 …PINGROUP(sys_clk_req_pz5, SYSCLK, RSVD2, RSVD3, RSVD4, 0x3320, N, …

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