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Searched refs:SYSC_REG_CLKCFG0 (Results 1 – 3 of 3) sorted by relevance

/linux-6.3-rc2/arch/mips/include/asm/mach-ralink/
A Dmt7620.h22 #define SYSC_REG_CLKCFG0 0x2c macro
/linux-6.3-rc2/drivers/clk/ralink/
A Dclk-mt7621.c22 #define SYSC_REG_CLKCFG0 0x2c macro
265 regmap_read(sysc, SYSC_REG_CLKCFG0, &clkcfg); in mt7621_cpu_recalc_rate()
/linux-6.3-rc2/arch/mips/ralink/
A Dmt7620.c83 reg = rt_sysc_r32(SYSC_REG_CLKCFG0); in mt7620_get_periph_rate()

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