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Searched refs:SYSC_REG_CPLL_CONFIG0 (Results 1 – 2 of 2) sorted by relevance

/linux-6.3-rc2/arch/mips/include/asm/mach-ralink/
A Dmt7620.h24 #define SYSC_REG_CPLL_CONFIG0 0x54 macro
/linux-6.3-rc2/arch/mips/ralink/
A Dmt7620.c99 reg = rt_sysc_r32(SYSC_REG_CPLL_CONFIG0); in mt7620_get_cpu_pll_rate()

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