Searched refs:TEGRA194_CLK_PLLA_OUT0 (Results 1 – 2 of 2) sorted by relevance
234 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;249 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;263 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;277 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;291 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;305 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;319 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;424 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;3122 <&bpmp TEGRA194_CLK_PLLA_OUT0>;3125 <&bpmp TEGRA194_CLK_PLLA_OUT0>,[all …]
110 #define TEGRA194_CLK_PLLA_OUT0 104 macro
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