Searched refs:TEGRA20_AC97_FIFO1_SCR (Results 1 – 2 of 2) sorted by relevance
145 regmap_update_bits(ac97->regmap, TEGRA20_AC97_FIFO1_SCR, in tegra20_ac97_start_playback()158 regmap_update_bits(ac97->regmap, TEGRA20_AC97_FIFO1_SCR, in tegra20_ac97_stop_playback()167 regmap_update_bits(ac97->regmap, TEGRA20_AC97_FIFO1_SCR, in tegra20_ac97_start_capture()174 regmap_update_bits(ac97->regmap, TEGRA20_AC97_FIFO1_SCR, in tegra20_ac97_stop_capture()252 case TEGRA20_AC97_FIFO1_SCR: in tegra20_ac97_wr_rd_reg()267 case TEGRA20_AC97_FIFO1_SCR: in tegra20_ac97_volatile_reg()
21 #define TEGRA20_AC97_FIFO1_SCR 0x1c macro
Completed in 5 milliseconds