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Searched refs:TEGRA30_CLK_PLL_P (Results 1 – 5 of 5) sorted by relevance

/linux-6.3-rc2/drivers/clk/tegra/
A Dclk-tegra30.c541 { .con_id = "pll_p", .dt_id = TEGRA30_CLK_PLL_P },
1200 { TEGRA30_CLK_UARTA, TEGRA30_CLK_PLL_P, 408000000, 0 },
1201 { TEGRA30_CLK_UARTB, TEGRA30_CLK_PLL_P, 408000000, 0 },
1217 { TEGRA30_CLK_SBC1, TEGRA30_CLK_PLL_P, 100000000, 0 },
1218 { TEGRA30_CLK_SBC2, TEGRA30_CLK_PLL_P, 100000000, 0 },
1219 { TEGRA30_CLK_SBC3, TEGRA30_CLK_PLL_P, 100000000, 0 },
1220 { TEGRA30_CLK_SBC4, TEGRA30_CLK_PLL_P, 100000000, 0 },
1221 { TEGRA30_CLK_SBC5, TEGRA30_CLK_PLL_P, 100000000, 0 },
1222 { TEGRA30_CLK_SBC6, TEGRA30_CLK_PLL_P, 100000000, 0 },
1238 { TEGRA30_CLK_HDA, TEGRA30_CLK_PLL_P, 102000000, 0 },
[all …]
/linux-6.3-rc2/include/dt-bindings/clock/
A Dtegra30-car.h206 #define TEGRA30_CLK_PLL_P 179 macro
/linux-6.3-rc2/arch/arm/boot/dts/
A Dtegra30.dtsi233 <&tegra_car TEGRA30_CLK_PLL_P>;
265 <&tegra_car TEGRA30_CLK_PLL_P>;
A Dtegra30-asus-transformer-common.dtsi112 assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_P>;
A Dtegra30-pegatron-chagall.dts94 assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_P>;

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