1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3  *  Register definitions specific to the A2 core
4  *
5  *  Copyright (C) 2008 Ben. Herrenschmidt (benh@kernel.crashing.org), IBM Corp.
6  */
7 
8 #ifndef __ASM_POWERPC_REG_A2_H__
9 #define __ASM_POWERPC_REG_A2_H__
10 
11 #include <asm/asm-const.h>
12 
13 #define SPRN_TENSR	0x1b5
14 #define SPRN_TENS	0x1b6	/* Thread ENable Set */
15 #define SPRN_TENC	0x1b7	/* Thread ENable Clear */
16 
17 #define SPRN_A2_CCR0	0x3f0	/* Core Configuration Register 0 */
18 #define SPRN_A2_CCR1	0x3f1	/* Core Configuration Register 1 */
19 #define SPRN_A2_CCR2	0x3f2	/* Core Configuration Register 2 */
20 #define SPRN_MMUCR0	0x3fc	/* MMU Control Register 0 */
21 #define SPRN_MMUCR1	0x3fd	/* MMU Control Register 1 */
22 #define SPRN_MMUCR2	0x3fe	/* MMU Control Register 2 */
23 #define SPRN_MMUCR3	0x3ff	/* MMU Control Register 3 */
24 
25 #define SPRN_IAR	0x372
26 
27 #define SPRN_IUCR0	0x3f3
28 #define IUCR0_ICBI_ACK	0x1000
29 
30 #define SPRN_XUCR0	0x3f6	/* Execution Unit Config Register 0 */
31 
32 #define A2_IERAT_SIZE	16
33 #define A2_DERAT_SIZE	32
34 
35 /* A2 MMUCR0 bits */
36 #define MMUCR0_ECL	0x80000000	/* Extended Class for TLB fills */
37 #define MMUCR0_TID_NZ	0x40000000	/* TID is non-zero */
38 #define MMUCR0_TS	0x10000000	/* Translation space for TLB fills */
39 #define MMUCR0_TGS	0x20000000	/* Guest space for TLB fills */
40 #define MMUCR0_TLBSEL	0x0c000000	/* TLB or ERAT target for TLB fills */
41 #define MMUCR0_TLBSEL_U	0x00000000	/*  TLBSEL = UTLB */
42 #define MMUCR0_TLBSEL_I	0x08000000	/*  TLBSEL = I-ERAT */
43 #define MMUCR0_TLBSEL_D	0x0c000000	/*  TLBSEL = D-ERAT */
44 #define MMUCR0_LOCKSRSH	0x02000000	/* Use TLB lock on tlbsx. */
45 #define MMUCR0_TID_MASK	0x000000ff	/* TID field */
46 
47 /* A2 MMUCR1 bits */
48 #define MMUCR1_IRRE		0x80000000	/* I-ERAT round robin enable */
49 #define MMUCR1_DRRE		0x40000000	/* D-ERAT round robin enable */
50 #define MMUCR1_REE		0x20000000	/* Reference Exception Enable*/
51 #define MMUCR1_CEE		0x10000000	/* Change exception enable */
52 #define MMUCR1_CSINV_ALL	0x00000000	/* Inval ERAT on all CS evts */
53 #define MMUCR1_CSINV_NISYNC	0x04000000	/* Inval ERAT on all ex isync*/
54 #define MMUCR1_CSINV_NEVER	0x0c000000	/* Don't inval ERAT on CS */
55 #define MMUCR1_ICTID		0x00080000	/* IERAT class field as TID */
56 #define MMUCR1_ITTID		0x00040000	/* IERAT thdid field as TID */
57 #define MMUCR1_DCTID		0x00020000	/* DERAT class field as TID */
58 #define MMUCR1_DTTID		0x00010000	/* DERAT thdid field as TID */
59 #define MMUCR1_DCCD		0x00008000	/* DERAT class ignore */
60 #define MMUCR1_TLBWE_BINV	0x00004000	/* back invalidate on tlbwe */
61 
62 /* A2 MMUCR2 bits */
63 #define MMUCR2_PSSEL_SHIFT	4
64 
65 /* A2 MMUCR3 bits */
66 #define MMUCR3_THID		0x0000000f	/* Thread ID */
67 
68 /* *** ERAT TLB bits definitions */
69 #define TLB0_EPN_MASK		ASM_CONST(0xfffffffffffff000)
70 #define TLB0_CLASS_MASK		ASM_CONST(0x0000000000000c00)
71 #define TLB0_CLASS_00		ASM_CONST(0x0000000000000000)
72 #define TLB0_CLASS_01		ASM_CONST(0x0000000000000400)
73 #define TLB0_CLASS_10		ASM_CONST(0x0000000000000800)
74 #define TLB0_CLASS_11		ASM_CONST(0x0000000000000c00)
75 #define TLB0_V			ASM_CONST(0x0000000000000200)
76 #define TLB0_X			ASM_CONST(0x0000000000000100)
77 #define TLB0_SIZE_MASK		ASM_CONST(0x00000000000000f0)
78 #define TLB0_SIZE_4K		ASM_CONST(0x0000000000000010)
79 #define TLB0_SIZE_64K		ASM_CONST(0x0000000000000030)
80 #define TLB0_SIZE_1M		ASM_CONST(0x0000000000000050)
81 #define TLB0_SIZE_16M		ASM_CONST(0x0000000000000070)
82 #define TLB0_SIZE_1G		ASM_CONST(0x00000000000000a0)
83 #define TLB0_THDID_MASK		ASM_CONST(0x000000000000000f)
84 #define TLB0_THDID_0		ASM_CONST(0x0000000000000001)
85 #define TLB0_THDID_1		ASM_CONST(0x0000000000000002)
86 #define TLB0_THDID_2		ASM_CONST(0x0000000000000004)
87 #define TLB0_THDID_3		ASM_CONST(0x0000000000000008)
88 #define TLB0_THDID_ALL		ASM_CONST(0x000000000000000f)
89 
90 #define TLB1_RESVATTR		ASM_CONST(0x00f0000000000000)
91 #define TLB1_U0			ASM_CONST(0x0008000000000000)
92 #define TLB1_U1			ASM_CONST(0x0004000000000000)
93 #define TLB1_U2			ASM_CONST(0x0002000000000000)
94 #define TLB1_U3			ASM_CONST(0x0001000000000000)
95 #define TLB1_R			ASM_CONST(0x0000800000000000)
96 #define TLB1_C			ASM_CONST(0x0000400000000000)
97 #define TLB1_RPN_MASK		ASM_CONST(0x000003fffffff000)
98 #define TLB1_W			ASM_CONST(0x0000000000000800)
99 #define TLB1_I			ASM_CONST(0x0000000000000400)
100 #define TLB1_M			ASM_CONST(0x0000000000000200)
101 #define TLB1_G			ASM_CONST(0x0000000000000100)
102 #define TLB1_E			ASM_CONST(0x0000000000000080)
103 #define TLB1_VF			ASM_CONST(0x0000000000000040)
104 #define TLB1_UX			ASM_CONST(0x0000000000000020)
105 #define TLB1_SX			ASM_CONST(0x0000000000000010)
106 #define TLB1_UW			ASM_CONST(0x0000000000000008)
107 #define TLB1_SW			ASM_CONST(0x0000000000000004)
108 #define TLB1_UR			ASM_CONST(0x0000000000000002)
109 #define TLB1_SR			ASM_CONST(0x0000000000000001)
110 
111 /* A2 erativax attributes definitions */
112 #define ERATIVAX_RS_IS_ALL		0x000
113 #define ERATIVAX_RS_IS_TID		0x040
114 #define ERATIVAX_RS_IS_CLASS		0x080
115 #define ERATIVAX_RS_IS_FULLMATCH	0x0c0
116 #define ERATIVAX_CLASS_00		0x000
117 #define ERATIVAX_CLASS_01		0x010
118 #define ERATIVAX_CLASS_10		0x020
119 #define ERATIVAX_CLASS_11		0x030
120 #define ERATIVAX_PSIZE_4K		(TLB_PSIZE_4K >> 1)
121 #define ERATIVAX_PSIZE_64K		(TLB_PSIZE_64K >> 1)
122 #define ERATIVAX_PSIZE_1M		(TLB_PSIZE_1M >> 1)
123 #define ERATIVAX_PSIZE_16M		(TLB_PSIZE_16M >> 1)
124 #define ERATIVAX_PSIZE_1G		(TLB_PSIZE_1G >> 1)
125 
126 /* A2 eratilx attributes definitions */
127 #define ERATILX_T_ALL			0
128 #define ERATILX_T_TID			1
129 #define ERATILX_T_TGS			2
130 #define ERATILX_T_FULLMATCH		3
131 #define ERATILX_T_CLASS0		4
132 #define ERATILX_T_CLASS1		5
133 #define ERATILX_T_CLASS2		6
134 #define ERATILX_T_CLASS3		7
135 
136 /* XUCR0 bits */
137 #define XUCR0_TRACE_UM_T0		0x40000000	/* Thread 0 */
138 #define XUCR0_TRACE_UM_T1		0x20000000	/* Thread 1 */
139 #define XUCR0_TRACE_UM_T2		0x10000000	/* Thread 2 */
140 #define XUCR0_TRACE_UM_T3		0x08000000	/* Thread 3 */
141 
142 /* A2 CCR0 register */
143 #define A2_CCR0_PME_DISABLED		0x00000000
144 #define A2_CCR0_PME_SLEEP		0x40000000
145 #define A2_CCR0_PME_RVW			0x80000000
146 #define A2_CCR0_PME_DISABLED2		0xc0000000
147 
148 /* A2 CCR2 register */
149 #define A2_CCR2_ERAT_ONLY_MODE		0x00000001
150 #define A2_CCR2_ENABLE_ICSWX		0x00000002
151 #define A2_CCR2_ENABLE_PC		0x20000000
152 #define A2_CCR2_ENABLE_TRACE		0x40000000
153 
154 #endif /* __ASM_POWERPC_REG_A2_H__ */
155