1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * MFD driver for twl6040
4  *
5  * Authors:     Jorge Eduardo Candelaria <jorge.candelaria@ti.com>
6  *              Misael Lopez Cruz <misael.lopez@ti.com>
7  *
8  * Copyright:   (C) 2011 Texas Instruments, Inc.
9  */
10 
11 #ifndef __TWL6040_CODEC_H__
12 #define __TWL6040_CODEC_H__
13 
14 #include <linux/interrupt.h>
15 #include <linux/mfd/core.h>
16 #include <linux/regulator/consumer.h>
17 #include <linux/clk.h>
18 
19 #define TWL6040_REG_ASICID		0x01
20 #define TWL6040_REG_ASICREV		0x02
21 #define TWL6040_REG_INTID		0x03
22 #define TWL6040_REG_INTMR		0x04
23 #define TWL6040_REG_NCPCTL		0x05
24 #define TWL6040_REG_LDOCTL		0x06
25 #define TWL6040_REG_HPPLLCTL		0x07
26 #define TWL6040_REG_LPPLLCTL		0x08
27 #define TWL6040_REG_LPPLLDIV		0x09
28 #define TWL6040_REG_AMICBCTL		0x0A
29 #define TWL6040_REG_DMICBCTL		0x0B
30 #define TWL6040_REG_MICLCTL		0x0C
31 #define TWL6040_REG_MICRCTL		0x0D
32 #define TWL6040_REG_MICGAIN		0x0E
33 #define TWL6040_REG_LINEGAIN		0x0F
34 #define TWL6040_REG_HSLCTL		0x10
35 #define TWL6040_REG_HSRCTL		0x11
36 #define TWL6040_REG_HSGAIN		0x12
37 #define TWL6040_REG_EARCTL		0x13
38 #define TWL6040_REG_HFLCTL		0x14
39 #define TWL6040_REG_HFLGAIN		0x15
40 #define TWL6040_REG_HFRCTL		0x16
41 #define TWL6040_REG_HFRGAIN		0x17
42 #define TWL6040_REG_VIBCTLL		0x18
43 #define TWL6040_REG_VIBDATL		0x19
44 #define TWL6040_REG_VIBCTLR		0x1A
45 #define TWL6040_REG_VIBDATR		0x1B
46 #define TWL6040_REG_HKCTL1		0x1C
47 #define TWL6040_REG_HKCTL2		0x1D
48 #define TWL6040_REG_GPOCTL		0x1E
49 #define TWL6040_REG_ALB			0x1F
50 #define TWL6040_REG_DLB			0x20
51 #define TWL6040_REG_TRIM1		0x28
52 #define TWL6040_REG_TRIM2		0x29
53 #define TWL6040_REG_TRIM3		0x2A
54 #define TWL6040_REG_HSOTRIM		0x2B
55 #define TWL6040_REG_HFOTRIM		0x2C
56 #define TWL6040_REG_ACCCTL		0x2D
57 #define TWL6040_REG_STATUS		0x2E
58 
59 /* INTID (0x03) fields */
60 
61 #define TWL6040_THINT			0x01
62 #define TWL6040_PLUGINT			0x02
63 #define TWL6040_UNPLUGINT		0x04
64 #define TWL6040_HOOKINT			0x08
65 #define TWL6040_HFINT			0x10
66 #define TWL6040_VIBINT			0x20
67 #define TWL6040_READYINT		0x40
68 
69 /* INTMR (0x04) fields */
70 
71 #define TWL6040_THMSK			0x01
72 #define TWL6040_PLUGMSK			0x02
73 #define TWL6040_HOOKMSK			0x08
74 #define TWL6040_HFMSK			0x10
75 #define TWL6040_VIBMSK			0x20
76 #define TWL6040_READYMSK		0x40
77 #define TWL6040_ALLINT_MSK		0x7B
78 
79 /* NCPCTL (0x05) fields */
80 
81 #define TWL6040_NCPENA			0x01
82 #define TWL6040_NCPOPEN			0x40
83 
84 /* LDOCTL (0x06) fields */
85 
86 #define TWL6040_LSLDOENA		0x01
87 #define TWL6040_HSLDOENA		0x04
88 #define TWL6040_REFENA			0x40
89 #define TWL6040_OSCENA			0x80
90 
91 /* HPPLLCTL (0x07) fields */
92 
93 #define TWL6040_HPLLENA			0x01
94 #define TWL6040_HPLLRST			0x02
95 #define TWL6040_HPLLBP			0x04
96 #define TWL6040_HPLLSQRENA		0x08
97 #define TWL6040_MCLK_12000KHZ		(0 << 5)
98 #define TWL6040_MCLK_19200KHZ		(1 << 5)
99 #define TWL6040_MCLK_26000KHZ		(2 << 5)
100 #define TWL6040_MCLK_38400KHZ		(3 << 5)
101 #define TWL6040_MCLK_MSK		0x60
102 
103 /* LPPLLCTL (0x08) fields */
104 
105 #define TWL6040_LPLLENA			0x01
106 #define TWL6040_LPLLRST			0x02
107 #define TWL6040_LPLLSEL			0x04
108 #define TWL6040_LPLLFIN			0x08
109 #define TWL6040_HPLLSEL			0x10
110 
111 /* HSLCTL/R (0x10/0x11) fields */
112 
113 #define TWL6040_HSDACENA		(1 << 0)
114 #define TWL6040_HSDACMODE		(1 << 1)
115 #define TWL6040_HSDRVENA		(1 << 2)
116 #define TWL6040_HSDRVMODE		(1 << 3)
117 
118 /* HFLCTL/R (0x14/0x16) fields */
119 
120 #define TWL6040_HFDACENA		(1 << 0)
121 #define TWL6040_HFPGAENA		(1 << 1)
122 #define TWL6040_HFDRVENA		(1 << 4)
123 #define TWL6040_HFSWENA			(1 << 6)
124 
125 /* VIBCTLL/R (0x18/0x1A) fields */
126 
127 #define TWL6040_VIBENA			(1 << 0)
128 #define TWL6040_VIBSEL			(1 << 1)
129 #define TWL6040_VIBCTRL			(1 << 2)
130 #define TWL6040_VIBCTRL_P		(1 << 3)
131 #define TWL6040_VIBCTRL_N		(1 << 4)
132 
133 /* VIBDATL/R (0x19/0x1B) fields */
134 
135 #define TWL6040_VIBDAT_MAX		0x64
136 
137 /* GPOCTL (0x1E) fields */
138 
139 #define TWL6040_GPO1			0x01
140 #define TWL6040_GPO2			0x02
141 #define TWL6040_GPO3			0x04
142 
143 /* ACCCTL (0x2D) fields */
144 
145 #define TWL6040_I2CSEL			0x01
146 #define TWL6040_RESETSPLIT		0x04
147 #define TWL6040_INTCLRMODE		0x08
148 #define TWL6040_I2CMODE(x)		((x & 0x3) << 4)
149 
150 /* STATUS (0x2E) fields */
151 
152 #define TWL6040_PLUGCOMP		0x02
153 #define TWL6040_VIBLOCDET		0x10
154 #define TWL6040_VIBROCDET		0x20
155 #define TWL6040_TSHUTDET                0x40
156 
157 #define TWL6040_CELLS			4
158 
159 #define TWL6040_REV_ES1_0		0x00
160 #define TWL6040_REV_ES1_1		0x01 /* Rev ES1.1 and ES1.2 */
161 #define TWL6040_REV_ES1_3		0x02
162 #define TWL6041_REV_ES2_0		0x10
163 
164 #define TWL6040_IRQ_TH			0
165 #define TWL6040_IRQ_PLUG		1
166 #define TWL6040_IRQ_HOOK		2
167 #define TWL6040_IRQ_HF			3
168 #define TWL6040_IRQ_VIB			4
169 #define TWL6040_IRQ_READY		5
170 
171 /* PLL selection */
172 #define TWL6040_SYSCLK_SEL_LPPLL	0
173 #define TWL6040_SYSCLK_SEL_HPPLL	1
174 
175 #define TWL6040_GPO_MAX	3
176 
177 struct gpio_desc;
178 struct regmap;
179 struct regmap_irq_chips_data;
180 
181 struct twl6040 {
182 	struct device *dev;
183 	struct regmap *regmap;
184 	struct regmap_irq_chip_data *irq_data;
185 	struct regulator_bulk_data supplies[2]; /* supplies for vio, v2v1 */
186 	struct clk *clk32k;
187 	struct clk *mclk;
188 	struct mutex mutex;
189 	struct mutex irq_mutex;
190 	struct mfd_cell cells[TWL6040_CELLS];
191 	struct completion ready;
192 
193 	struct gpio_desc *audpwron;
194 	int power_count;
195 	int rev;
196 
197 	/* PLL configuration */
198 	int pll;
199 	unsigned int sysclk_rate;
200 	unsigned int mclk_rate;
201 
202 	unsigned int irq;
203 	unsigned int irq_ready;
204 	unsigned int irq_th;
205 };
206 
207 int twl6040_reg_read(struct twl6040 *twl6040, unsigned int reg);
208 int twl6040_reg_write(struct twl6040 *twl6040, unsigned int reg,
209 		      u8 val);
210 int twl6040_set_bits(struct twl6040 *twl6040, unsigned int reg,
211 		     u8 mask);
212 int twl6040_clear_bits(struct twl6040 *twl6040, unsigned int reg,
213 		       u8 mask);
214 int twl6040_power(struct twl6040 *twl6040, int on);
215 int twl6040_set_pll(struct twl6040 *twl6040, int pll_id,
216 		    unsigned int freq_in, unsigned int freq_out);
217 int twl6040_get_pll(struct twl6040 *twl6040);
218 unsigned int twl6040_get_sysclk(struct twl6040 *twl6040);
219 
220 /* Get the combined status of the vibra control register */
221 int twl6040_get_vibralr_status(struct twl6040 *twl6040);
222 
twl6040_get_revid(struct twl6040 * twl6040)223 static inline int twl6040_get_revid(struct twl6040 *twl6040)
224 {
225 	return twl6040->rev;
226 }
227 
228 
229 #endif  /* End of __TWL6040_CODEC_H__ */
230