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Searched refs:VC4_SET_FIELD (Results 1 – 13 of 13) sorted by relevance

/linux-6.3-rc2/drivers/gpu/drm/vc4/
A Dvc4_hdmi_phy.c407 VC4_SET_FIELD(phy_get_rm_offset(vco_freq), in vc5_hdmi_phy_init()
433 VC4_SET_FIELD(2, VC4_HDMI_RM_FORMAT_SHIFT)); in vc5_hdmi_phy_init()
446 VC4_SET_FIELD(phy_get_cp_current(vco_freq), in vc5_hdmi_phy_init()
448 VC4_SET_FIELD(1, VC4_HDMI_TX_PHY_CTL_3_CP) | in vc5_hdmi_phy_init()
450 VC4_SET_FIELD(3, VC4_HDMI_TX_PHY_CTL_3_CZ) | in vc5_hdmi_phy_init()
451 VC4_SET_FIELD(4, VC4_HDMI_TX_PHY_CTL_3_RP) | in vc5_hdmi_phy_init()
487 VC4_SET_FIELD(chan0_settings->res_sel_data, in vc5_hdmi_phy_init()
489 VC4_SET_FIELD(chan1_settings->res_sel_data, in vc5_hdmi_phy_init()
491 VC4_SET_FIELD(chan2_settings->res_sel_data, in vc5_hdmi_phy_init()
493 VC4_SET_FIELD(clock_settings->res_sel_data, in vc5_hdmi_phy_init()
[all …]
A Dvc4_dsi.c948 VC4_SET_FIELD(7, DSI_PHY_AFEC0_CTATADJ)); in vc4_dsi_bridge_pre_enable()
967 VC4_SET_FIELD(7, DSI_PHY_AFEC0_CTATADJ) | in vc4_dsi_bridge_pre_enable()
1033 VC4_SET_FIELD(dsi_hs_timing(ui_ns, 0, 8), in vc4_dsi_bridge_pre_enable()
1062 VC4_SET_FIELD(0, DSI_HS_DLT4_ANLAT)); in vc4_dsi_bridge_pre_enable()
1081 VC4_SET_FIELD(lpx, DSI_HS_DLT6_LP_LPX)); in vc4_dsi_bridge_pre_enable()
1084 VC4_SET_FIELD(dsi_esc_timing(1000000), in vc4_dsi_bridge_pre_enable()
1135 VC4_SET_FIELD(dsi->divider, in vc4_dsi_bridge_pre_enable()
1188 pkth |= VC4_SET_FIELD(packet.header[1] | in vc4_dsi_host_transfer()
1217 pktc |= VC4_SET_FIELD(DSI_TXPKT1C_CMD_CTRL_RX, in vc4_dsi_host_transfer()
1220 pktc |= VC4_SET_FIELD(DSI_TXPKT1C_CMD_CTRL_TX, in vc4_dsi_host_transfer()
[all …]
A Dvc4_plane.c1084 VC4_SET_FIELD(vc4_state->crtc_w, in vc4_plane_mode_set()
1086 VC4_SET_FIELD(vc4_state->crtc_h, in vc4_plane_mode_set()
1095 VC4_SET_FIELD(vc4_state->src_w[0], in vc4_plane_mode_set()
1097 VC4_SET_FIELD(vc4_state->src_h[0], in vc4_plane_mode_set()
1122 VC4_SET_FIELD(vc4_state->crtc_x, in vc4_plane_mode_set()
1126 VC4_SET_FIELD(vc4_state->crtc_y, in vc4_plane_mode_set()
1132 VC4_SET_FIELD(state->alpha >> 4, in vc4_plane_mode_set()
1142 VC4_SET_FIELD(vc4_state->crtc_w, in vc4_plane_mode_set()
1144 VC4_SET_FIELD(vc4_state->crtc_h, in vc4_plane_mode_set()
1151 VC4_SET_FIELD(vc4_state->src_w[0], in vc4_plane_mode_set()
[all …]
A Dvc4_dpi.c163 dpi_c |= VC4_SET_FIELD(DPI_FORMAT_18BIT_666_RGB_1, DPI_FORMAT); in vc4_dpi_encoder_enable()
173 dpi_c |= VC4_SET_FIELD(DPI_FORMAT_24BIT_888_RGB, in vc4_dpi_encoder_enable()
177 dpi_c |= VC4_SET_FIELD(DPI_FORMAT_24BIT_888_RGB, in vc4_dpi_encoder_enable()
179 dpi_c |= VC4_SET_FIELD(DPI_ORDER_BGR, in vc4_dpi_encoder_enable()
183 dpi_c |= VC4_SET_FIELD(DPI_ORDER_BGR, DPI_ORDER); in vc4_dpi_encoder_enable()
186 dpi_c |= VC4_SET_FIELD(DPI_FORMAT_18BIT_666_RGB_2, in vc4_dpi_encoder_enable()
190 dpi_c |= VC4_SET_FIELD(DPI_ORDER_BGR, DPI_ORDER); in vc4_dpi_encoder_enable()
193 dpi_c |= VC4_SET_FIELD(DPI_FORMAT_18BIT_666_RGB_1, in vc4_dpi_encoder_enable()
197 dpi_c |= VC4_SET_FIELD(DPI_FORMAT_16BIT_565_RGB_1, in vc4_dpi_encoder_enable()
201 dpi_c |= VC4_SET_FIELD(DPI_FORMAT_16BIT_565_RGB_2, in vc4_dpi_encoder_enable()
A Dvc4_kms.c149 VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[0]), in vc4_ctm_commit()
151 VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[3]), in vc4_ctm_commit()
153 VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[6]), in vc4_ctm_commit()
156 VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[1]), in vc4_ctm_commit()
158 VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[4]), in vc4_ctm_commit()
160 VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[7]), in vc4_ctm_commit()
245 dsp3_mux = VC4_SET_FIELD(3, SCALER_DISPCTRL_DSP3_MUX); in vc4_hvs_pv_muxing_commit()
283 VC4_SET_FIELD(mux, SCALER_DISPECTRL_DSP2_MUX)); in vc5_hvs_pv_muxing_commit()
295 VC4_SET_FIELD(mux, SCALER_DISPCTRL_DSP3_MUX)); in vc5_hvs_pv_muxing_commit()
307 VC4_SET_FIELD(mux, SCALER_DISPEOLN_DSP4_MUX)); in vc5_hvs_pv_muxing_commit()
[all …]
A Dvc4_hdmi.c1251 VC4_SET_FIELD(mode->crtc_vtotal - in vc4_hdmi_set_timings()
1270 VC4_SET_FIELD((mode->htotal - in vc4_hdmi_set_timings()
1273 VC4_SET_FIELD((mode->hsync_end - in vc4_hdmi_set_timings()
1276 VC4_SET_FIELD((mode->hsync_start - in vc4_hdmi_set_timings()
1318 VC4_SET_FIELD(mode->crtc_vtotal - in vc5_hdmi_set_timings()
1336 VC4_SET_FIELD((mode->hsync_start - in vc5_hdmi_set_timings()
1341 VC4_SET_FIELD((mode->htotal - in vc5_hdmi_set_timings()
1344 VC4_SET_FIELD((mode->hsync_end - in vc5_hdmi_set_timings()
2085 VC4_SET_FIELD(n, VC4_HD_MAI_SMP_N) | in vc4_hdmi_audio_set_mai_clock()
2327 VC4_SET_FIELD(mai_sample_rate, in vc4_hdmi_audio_prepare()
[all …]
A Dvc4_crtc.c278 ret |= VC4_SET_FIELD((level >> 6), in vc4_crtc_get_fifo_full_level_bits()
281 return ret | VC4_SET_FIELD(level & 0x3f, in vc4_crtc_get_fifo_full_level_bits()
394 VC4_SET_FIELD(vert_bp_even, PV_VERTA_VBP) | in vc4_crtc_config_pv()
395 VC4_SET_FIELD(vert_sync, PV_VERTA_VSYNC)); in vc4_crtc_config_pv()
397 VC4_SET_FIELD(vert_fp_even, PV_VERTB_VFP) | in vc4_crtc_config_pv()
409 : VC4_SET_FIELD(field_delay, in vc4_crtc_config_pv()
421 VC4_SET_FIELD(vert_bp, PV_VERTA_VBP) | in vc4_crtc_config_pv()
422 VC4_SET_FIELD(vert_sync, PV_VERTA_VSYNC)); in vc4_crtc_config_pv()
424 VC4_SET_FIELD(vert_fp, PV_VERTB_VFP) | in vc4_crtc_config_pv()
437 VC4_SET_FIELD(format, PV_CONTROL_FORMAT) | in vc4_crtc_config_pv()
[all …]
A Dvc4_hvs.c376 dispctrl |= VC4_SET_FIELD(mode->hdisplay, in vc4_hvs_init_channel()
378 VC4_SET_FIELD(mode->vdisplay, in vc4_hvs_init_channel()
383 dispctrl |= VC4_SET_FIELD(mode->hdisplay, in vc4_hvs_init_channel()
385 VC4_SET_FIELD(mode->vdisplay, in vc4_hvs_init_channel()
901 reg | VC4_SET_FIELD(0, SCALER_DISPECTRL_DSP2_MUX)); in vc4_hvs_bind()
906 reg | VC4_SET_FIELD(3, SCALER_DISPCTRL_DSP3_MUX)); in vc4_hvs_bind()
911 reg | VC4_SET_FIELD(3, SCALER_DISPEOLN_DSP4_MUX)); in vc4_hvs_bind()
916 reg | VC4_SET_FIELD(3, SCALER_DISPDITHER_DSP5_MUX)); in vc4_hvs_bind()
961 dispctrl |= VC4_SET_FIELD(2, SCALER_DISPCTRL_PANIC0); in vc4_hvs_bind()
962 dispctrl |= VC4_SET_FIELD(2, SCALER_DISPCTRL_PANIC1); in vc4_hvs_bind()
[all …]
A Dvc4_txp.c315 VC4_SET_FIELD(0xf, TXP_BYTE_ENABLE) | in vc4_txp_connector_atomic_commit()
316 VC4_SET_FIELD(txp_fmts[i], TXP_FORMAT); in vc4_txp_connector_atomic_commit()
334 VC4_SET_FIELD(mode->hdisplay, TXP_WIDTH) | in vc4_txp_connector_atomic_commit()
335 VC4_SET_FIELD(mode->vdisplay, TXP_HEIGHT)); in vc4_txp_connector_atomic_commit()
A Dvc4_gem.c447 VC4_SET_FIELD(0xf, V3D_SLCACTL_T1CC) | in vc4_flush_caches()
448 VC4_SET_FIELD(0xf, V3D_SLCACTL_T0CC) | in vc4_flush_caches()
449 VC4_SET_FIELD(0xf, V3D_SLCACTL_UCC) | in vc4_flush_caches()
450 VC4_SET_FIELD(0xf, V3D_SLCACTL_ICC)); in vc4_flush_caches()
462 VC4_SET_FIELD(0xf, V3D_SLCACTL_T1CC) | in vc4_flush_texture_caches()
463 VC4_SET_FIELD(0xf, V3D_SLCACTL_T0CC)); in vc4_flush_texture_caches()
A Dvc4_validate.c417 VC4_SET_FIELD(VC4_BIN_CONFIG_ALLOC_INIT_BLOCK_SIZE_32, in validate_tile_binning_config()
419 VC4_SET_FIELD(VC4_BIN_CONFIG_ALLOC_BLOCK_SIZE_128, in validate_tile_binning_config()
A Dvc4_render_cl.c84 VC4_SET_FIELD(VC4_LOADSTORE_TILE_BUFFER_NONE, in vc4_store_before_load()
A Dvc4_regs.h14 #define VC4_SET_FIELD(value, field) \ macro

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