1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 #ifndef DC_TYPES_H_ 26 #define DC_TYPES_H_ 27 28 /* AND EdidUtility only needs a portion 29 * of this file, including the rest only 30 * causes additional issues. 31 */ 32 #include "os_types.h" 33 #include "fixed31_32.h" 34 #include "irq_types.h" 35 #include "dc_ddc_types.h" 36 #include "dc_dp_types.h" 37 #include "dc_hdmi_types.h" 38 #include "dc_hw_types.h" 39 #include "dal_types.h" 40 #include "grph_object_defs.h" 41 42 #ifdef CONFIG_DRM_AMD_DC_HDCP 43 #include "dm_cp_psp.h" 44 #endif 45 46 /* forward declarations */ 47 struct dc_plane_state; 48 struct dc_stream_state; 49 struct dc_link; 50 struct dc_sink; 51 struct dal; 52 struct dc_dmub_srv; 53 54 /******************************** 55 * Environment definitions 56 ********************************/ 57 enum dce_environment { 58 DCE_ENV_PRODUCTION_DRV = 0, 59 /* Emulation on FPGA, in "Maximus" System. 60 * This environment enforces that *only* DC registers accessed. 61 * (access to non-DC registers will hang FPGA) */ 62 DCE_ENV_FPGA_MAXIMUS, 63 /* Emulation on real HW or on FPGA. Used by Diagnostics, enforces 64 * requirements of Diagnostics team. */ 65 DCE_ENV_DIAG, 66 /* 67 * Guest VM system, DC HW may exist but is not virtualized and 68 * should not be used. SW support for VDI only. 69 */ 70 DCE_ENV_VIRTUAL_HW 71 }; 72 73 /* Note: use these macro definitions instead of direct comparison! */ 74 #define IS_FPGA_MAXIMUS_DC(dce_environment) \ 75 (dce_environment == DCE_ENV_FPGA_MAXIMUS) 76 77 #define IS_DIAG_DC(dce_environment) \ 78 (IS_FPGA_MAXIMUS_DC(dce_environment) || (dce_environment == DCE_ENV_DIAG)) 79 80 struct dc_perf_trace { 81 unsigned long read_count; 82 unsigned long write_count; 83 unsigned long last_entry_read; 84 unsigned long last_entry_write; 85 }; 86 87 #define MAX_SURFACE_NUM 4 88 #define NUM_PIXEL_FORMATS 10 89 90 enum tiling_mode { 91 TILING_MODE_INVALID, 92 TILING_MODE_LINEAR, 93 TILING_MODE_TILED, 94 TILING_MODE_COUNT 95 }; 96 97 enum view_3d_format { 98 VIEW_3D_FORMAT_NONE = 0, 99 VIEW_3D_FORMAT_FRAME_SEQUENTIAL, 100 VIEW_3D_FORMAT_SIDE_BY_SIDE, 101 VIEW_3D_FORMAT_TOP_AND_BOTTOM, 102 VIEW_3D_FORMAT_COUNT, 103 VIEW_3D_FORMAT_FIRST = VIEW_3D_FORMAT_FRAME_SEQUENTIAL 104 }; 105 106 enum plane_stereo_format { 107 PLANE_STEREO_FORMAT_NONE = 0, 108 PLANE_STEREO_FORMAT_SIDE_BY_SIDE = 1, 109 PLANE_STEREO_FORMAT_TOP_AND_BOTTOM = 2, 110 PLANE_STEREO_FORMAT_FRAME_ALTERNATE = 3, 111 PLANE_STEREO_FORMAT_ROW_INTERLEAVED = 5, 112 PLANE_STEREO_FORMAT_COLUMN_INTERLEAVED = 6, 113 PLANE_STEREO_FORMAT_CHECKER_BOARD = 7 114 }; 115 116 /* TODO: Find way to calculate number of bits 117 * Please increase if pixel_format enum increases 118 * num from PIXEL_FORMAT_INDEX8 to PIXEL_FORMAT_444BPP32 119 */ 120 121 enum dc_edid_connector_type { 122 DC_EDID_CONNECTOR_UNKNOWN = 0, 123 DC_EDID_CONNECTOR_ANALOG = 1, 124 DC_EDID_CONNECTOR_DIGITAL = 10, 125 DC_EDID_CONNECTOR_DVI = 11, 126 DC_EDID_CONNECTOR_HDMIA = 12, 127 DC_EDID_CONNECTOR_MDDI = 14, 128 DC_EDID_CONNECTOR_DISPLAYPORT = 15 129 }; 130 131 enum dc_edid_status { 132 EDID_OK, 133 EDID_BAD_INPUT, 134 EDID_NO_RESPONSE, 135 EDID_BAD_CHECKSUM, 136 EDID_THE_SAME, 137 EDID_FALL_BACK, 138 EDID_PARTIAL_VALID, 139 }; 140 141 enum act_return_status { 142 ACT_SUCCESS, 143 ACT_LINK_LOST, 144 ACT_FAILED 145 }; 146 147 /* audio capability from EDID*/ 148 struct dc_cea_audio_mode { 149 uint8_t format_code; /* ucData[0] [6:3]*/ 150 uint8_t channel_count; /* ucData[0] [2:0]*/ 151 uint8_t sample_rate; /* ucData[1]*/ 152 union { 153 uint8_t sample_size; /* for LPCM*/ 154 /* for Audio Formats 2-8 (Max bit rate divided by 8 kHz)*/ 155 uint8_t max_bit_rate; 156 uint8_t audio_codec_vendor_specific; /* for Audio Formats 9-15*/ 157 }; 158 }; 159 160 struct dc_edid { 161 uint32_t length; 162 uint8_t raw_edid[DC_MAX_EDID_BUFFER_SIZE]; 163 }; 164 165 /* When speaker location data block is not available, DEFAULT_SPEAKER_LOCATION 166 * is used. In this case we assume speaker location are: front left, front 167 * right and front center. */ 168 #define DEFAULT_SPEAKER_LOCATION 5 169 170 #define DC_MAX_AUDIO_DESC_COUNT 16 171 172 #define AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS 20 173 174 union display_content_support { 175 unsigned int raw; 176 struct { 177 unsigned int valid_content_type :1; 178 unsigned int game_content :1; 179 unsigned int cinema_content :1; 180 unsigned int photo_content :1; 181 unsigned int graphics_content :1; 182 unsigned int reserved :27; 183 } bits; 184 }; 185 186 struct dc_panel_patch { 187 unsigned int dppowerup_delay; 188 unsigned int extra_t12_ms; 189 unsigned int extra_delay_backlight_off; 190 unsigned int extra_t7_ms; 191 unsigned int skip_scdc_overwrite; 192 unsigned int delay_ignore_msa; 193 unsigned int disable_fec; 194 unsigned int extra_t3_ms; 195 unsigned int max_dsc_target_bpp_limit; 196 unsigned int embedded_tiled_slave; 197 unsigned int disable_fams; 198 unsigned int skip_avmute; 199 unsigned int mst_start_top_delay; 200 }; 201 202 struct dc_edid_caps { 203 /* sink identification */ 204 uint16_t manufacturer_id; 205 uint16_t product_id; 206 uint32_t serial_number; 207 uint8_t manufacture_week; 208 uint8_t manufacture_year; 209 uint8_t display_name[AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS]; 210 211 /* audio caps */ 212 uint8_t speaker_flags; 213 uint32_t audio_mode_count; 214 struct dc_cea_audio_mode audio_modes[DC_MAX_AUDIO_DESC_COUNT]; 215 uint32_t audio_latency; 216 uint32_t video_latency; 217 218 union display_content_support content_support; 219 220 uint8_t qs_bit; 221 uint8_t qy_bit; 222 223 uint32_t max_tmds_clk_mhz; 224 225 /*HDMI 2.0 caps*/ 226 bool lte_340mcsc_scramble; 227 228 bool edid_hdmi; 229 bool hdr_supported; 230 231 struct dc_panel_patch panel_patch; 232 }; 233 234 struct dc_mode_flags { 235 /* note: part of refresh rate flag*/ 236 uint32_t INTERLACE :1; 237 /* native display timing*/ 238 uint32_t NATIVE :1; 239 /* preferred is the recommended mode, one per display */ 240 uint32_t PREFERRED :1; 241 /* true if this mode should use reduced blanking timings 242 *_not_ related to the Reduced Blanking adjustment*/ 243 uint32_t REDUCED_BLANKING :1; 244 /* note: part of refreshrate flag*/ 245 uint32_t VIDEO_OPTIMIZED_RATE :1; 246 /* should be reported to upper layers as mode_flags*/ 247 uint32_t PACKED_PIXEL_FORMAT :1; 248 /*< preferred view*/ 249 uint32_t PREFERRED_VIEW :1; 250 /* this timing should be used only in tiled mode*/ 251 uint32_t TILED_MODE :1; 252 uint32_t DSE_MODE :1; 253 /* Refresh rate divider when Miracast sink is using a 254 different rate than the output display device 255 Must be zero for wired displays and non-zero for 256 Miracast displays*/ 257 uint32_t MIRACAST_REFRESH_DIVIDER; 258 }; 259 260 261 enum dc_timing_source { 262 TIMING_SOURCE_UNDEFINED, 263 264 /* explicitly specifed by user, most important*/ 265 TIMING_SOURCE_USER_FORCED, 266 TIMING_SOURCE_USER_OVERRIDE, 267 TIMING_SOURCE_CUSTOM, 268 TIMING_SOURCE_EXPLICIT, 269 270 /* explicitly specified by the display device, more important*/ 271 TIMING_SOURCE_EDID_CEA_SVD_3D, 272 TIMING_SOURCE_EDID_CEA_SVD_PREFERRED, 273 TIMING_SOURCE_EDID_CEA_SVD_420, 274 TIMING_SOURCE_EDID_DETAILED, 275 TIMING_SOURCE_EDID_ESTABLISHED, 276 TIMING_SOURCE_EDID_STANDARD, 277 TIMING_SOURCE_EDID_CEA_SVD, 278 TIMING_SOURCE_EDID_CVT_3BYTE, 279 TIMING_SOURCE_EDID_4BYTE, 280 TIMING_SOURCE_EDID_CEA_DISPLAYID_VTDB, 281 TIMING_SOURCE_EDID_CEA_RID, 282 TIMING_SOURCE_VBIOS, 283 TIMING_SOURCE_CV, 284 TIMING_SOURCE_TV, 285 TIMING_SOURCE_HDMI_VIC, 286 287 /* implicitly specified by display device, still safe but less important*/ 288 TIMING_SOURCE_DEFAULT, 289 290 /* only used for custom base modes */ 291 TIMING_SOURCE_CUSTOM_BASE, 292 293 /* these timing might not work, least important*/ 294 TIMING_SOURCE_RANGELIMIT, 295 TIMING_SOURCE_OS_FORCED, 296 TIMING_SOURCE_IMPLICIT, 297 298 /* only used by default mode list*/ 299 TIMING_SOURCE_BASICMODE, 300 301 TIMING_SOURCE_COUNT 302 }; 303 304 305 struct stereo_3d_features { 306 bool supported ; 307 bool allTimings ; 308 bool cloneMode ; 309 bool scaling ; 310 bool singleFrameSWPacked; 311 }; 312 313 enum dc_timing_support_method { 314 TIMING_SUPPORT_METHOD_UNDEFINED, 315 TIMING_SUPPORT_METHOD_EXPLICIT, 316 TIMING_SUPPORT_METHOD_IMPLICIT, 317 TIMING_SUPPORT_METHOD_NATIVE 318 }; 319 320 struct dc_mode_info { 321 uint32_t pixel_width; 322 uint32_t pixel_height; 323 uint32_t field_rate; 324 /* Vertical refresh rate for progressive modes. 325 * Field rate for interlaced modes.*/ 326 327 enum dc_timing_standard timing_standard; 328 enum dc_timing_source timing_source; 329 struct dc_mode_flags flags; 330 }; 331 332 enum dc_power_state { 333 DC_POWER_STATE_ON = 1, 334 DC_POWER_STATE_STANDBY, 335 DC_POWER_STATE_SUSPEND, 336 DC_POWER_STATE_OFF 337 }; 338 339 /* DC PowerStates */ 340 enum dc_video_power_state { 341 DC_VIDEO_POWER_UNSPECIFIED = 0, 342 DC_VIDEO_POWER_ON = 1, 343 DC_VIDEO_POWER_STANDBY, 344 DC_VIDEO_POWER_SUSPEND, 345 DC_VIDEO_POWER_OFF, 346 DC_VIDEO_POWER_HIBERNATE, 347 DC_VIDEO_POWER_SHUTDOWN, 348 DC_VIDEO_POWER_ULPS, /* BACO or Ultra-Light-Power-State */ 349 DC_VIDEO_POWER_AFTER_RESET, 350 DC_VIDEO_POWER_MAXIMUM 351 }; 352 353 enum dc_acpi_cm_power_state { 354 DC_ACPI_CM_POWER_STATE_D0 = 1, 355 DC_ACPI_CM_POWER_STATE_D1 = 2, 356 DC_ACPI_CM_POWER_STATE_D2 = 4, 357 DC_ACPI_CM_POWER_STATE_D3 = 8 358 }; 359 360 enum dc_connection_type { 361 dc_connection_none, 362 dc_connection_single, 363 dc_connection_mst_branch, 364 dc_connection_sst_branch 365 }; 366 367 struct dc_csc_adjustments { 368 struct fixed31_32 contrast; 369 struct fixed31_32 saturation; 370 struct fixed31_32 brightness; 371 struct fixed31_32 hue; 372 }; 373 374 /* Scaling format */ 375 enum scaling_transformation { 376 SCALING_TRANSFORMATION_UNINITIALIZED, 377 SCALING_TRANSFORMATION_IDENTITY = 0x0001, 378 SCALING_TRANSFORMATION_CENTER_TIMING = 0x0002, 379 SCALING_TRANSFORMATION_FULL_SCREEN_SCALE = 0x0004, 380 SCALING_TRANSFORMATION_PRESERVE_ASPECT_RATIO_SCALE = 0x0008, 381 SCALING_TRANSFORMATION_DAL_DECIDE = 0x0010, 382 SCALING_TRANSFORMATION_INVALID = 0x80000000, 383 384 /* Flag the first and last */ 385 SCALING_TRANSFORMATION_BEGING = SCALING_TRANSFORMATION_IDENTITY, 386 SCALING_TRANSFORMATION_END = 387 SCALING_TRANSFORMATION_PRESERVE_ASPECT_RATIO_SCALE 388 }; 389 390 enum display_content_type { 391 DISPLAY_CONTENT_TYPE_NO_DATA = 0, 392 DISPLAY_CONTENT_TYPE_GRAPHICS = 1, 393 DISPLAY_CONTENT_TYPE_PHOTO = 2, 394 DISPLAY_CONTENT_TYPE_CINEMA = 4, 395 DISPLAY_CONTENT_TYPE_GAME = 8 396 }; 397 398 enum cm_gamut_adjust_type { 399 CM_GAMUT_ADJUST_TYPE_BYPASS = 0, 400 CM_GAMUT_ADJUST_TYPE_HW, /* without adjustments */ 401 CM_GAMUT_ADJUST_TYPE_SW /* use adjustments */ 402 }; 403 404 struct cm_grph_csc_adjustment { 405 struct fixed31_32 temperature_matrix[12]; 406 enum cm_gamut_adjust_type gamut_adjust_type; 407 enum cm_gamut_coef_format gamut_coef_format; 408 }; 409 410 /* writeback */ 411 struct dwb_stereo_params { 412 bool stereo_enabled; /* false: normal mode, true: 3D stereo */ 413 enum dwb_stereo_type stereo_type; /* indicates stereo format */ 414 bool stereo_polarity; /* indicates left eye or right eye comes first in stereo mode */ 415 enum dwb_stereo_eye_select stereo_eye_select; /* indicate which eye should be captured */ 416 }; 417 418 struct dc_dwb_cnv_params { 419 unsigned int src_width; /* input active width */ 420 unsigned int src_height; /* input active height (half-active height in interlaced mode) */ 421 unsigned int crop_width; /* cropped window width at cnv output */ 422 bool crop_en; /* window cropping enable in cnv */ 423 unsigned int crop_height; /* cropped window height at cnv output */ 424 unsigned int crop_x; /* cropped window start x value at cnv output */ 425 unsigned int crop_y; /* cropped window start y value at cnv output */ 426 enum dwb_cnv_out_bpc cnv_out_bpc; /* cnv output pixel depth - 8bpc or 10bpc */ 427 enum dwb_out_format fc_out_format; /* dwb output pixel format - 2101010 or 16161616 and ARGB or RGBA */ 428 enum dwb_out_denorm out_denorm_mode;/* dwb output denormalization mode */ 429 unsigned int out_max_pix_val;/* pixel values greater than out_max_pix_val are clamped to out_max_pix_val */ 430 unsigned int out_min_pix_val;/* pixel values less than out_min_pix_val are clamped to out_min_pix_val */ 431 }; 432 433 struct dc_dwb_params { 434 unsigned int dwbscl_black_color; /* must be in FP1.5.10 */ 435 unsigned int hdr_mult; /* must be in FP1.6.12 */ 436 struct cm_grph_csc_adjustment csc_params; 437 struct dwb_stereo_params stereo_params; 438 struct dc_dwb_cnv_params cnv_params; /* CNV source size and cropping window parameters */ 439 unsigned int dest_width; /* Destination width */ 440 unsigned int dest_height; /* Destination height */ 441 enum dwb_scaler_mode out_format; /* default = YUV420 - TODO: limit this to 0 and 1 on dcn3 */ 442 enum dwb_output_depth output_depth; /* output pixel depth - 8bpc or 10bpc */ 443 enum dwb_capture_rate capture_rate; /* controls the frame capture rate */ 444 struct scaling_taps scaler_taps; /* Scaling taps */ 445 enum dwb_subsample_position subsample_position; 446 struct dc_transfer_func *out_transfer_func; 447 }; 448 449 /* audio*/ 450 451 union audio_sample_rates { 452 struct sample_rates { 453 uint8_t RATE_32:1; 454 uint8_t RATE_44_1:1; 455 uint8_t RATE_48:1; 456 uint8_t RATE_88_2:1; 457 uint8_t RATE_96:1; 458 uint8_t RATE_176_4:1; 459 uint8_t RATE_192:1; 460 } rate; 461 462 uint8_t all; 463 }; 464 465 struct audio_speaker_flags { 466 uint32_t FL_FR:1; 467 uint32_t LFE:1; 468 uint32_t FC:1; 469 uint32_t RL_RR:1; 470 uint32_t RC:1; 471 uint32_t FLC_FRC:1; 472 uint32_t RLC_RRC:1; 473 uint32_t SUPPORT_AI:1; 474 }; 475 476 struct audio_speaker_info { 477 uint32_t ALLSPEAKERS:7; 478 uint32_t SUPPORT_AI:1; 479 }; 480 481 482 struct audio_info_flags { 483 484 union { 485 486 struct audio_speaker_flags speaker_flags; 487 struct audio_speaker_info info; 488 489 uint8_t all; 490 }; 491 }; 492 493 enum audio_format_code { 494 AUDIO_FORMAT_CODE_FIRST = 1, 495 AUDIO_FORMAT_CODE_LINEARPCM = AUDIO_FORMAT_CODE_FIRST, 496 497 AUDIO_FORMAT_CODE_AC3, 498 /*Layers 1 & 2 */ 499 AUDIO_FORMAT_CODE_MPEG1, 500 /*MPEG1 Layer 3 */ 501 AUDIO_FORMAT_CODE_MP3, 502 /*multichannel */ 503 AUDIO_FORMAT_CODE_MPEG2, 504 AUDIO_FORMAT_CODE_AAC, 505 AUDIO_FORMAT_CODE_DTS, 506 AUDIO_FORMAT_CODE_ATRAC, 507 AUDIO_FORMAT_CODE_1BITAUDIO, 508 AUDIO_FORMAT_CODE_DOLBYDIGITALPLUS, 509 AUDIO_FORMAT_CODE_DTS_HD, 510 AUDIO_FORMAT_CODE_MAT_MLP, 511 AUDIO_FORMAT_CODE_DST, 512 AUDIO_FORMAT_CODE_WMAPRO, 513 AUDIO_FORMAT_CODE_LAST, 514 AUDIO_FORMAT_CODE_COUNT = 515 AUDIO_FORMAT_CODE_LAST - AUDIO_FORMAT_CODE_FIRST 516 }; 517 518 struct audio_mode { 519 /* ucData[0] [6:3] */ 520 enum audio_format_code format_code; 521 /* ucData[0] [2:0] */ 522 uint8_t channel_count; 523 /* ucData[1] */ 524 union audio_sample_rates sample_rates; 525 union { 526 /* for LPCM */ 527 uint8_t sample_size; 528 /* for Audio Formats 2-8 (Max bit rate divided by 8 kHz) */ 529 uint8_t max_bit_rate; 530 /* for Audio Formats 9-15 */ 531 uint8_t vendor_specific; 532 }; 533 }; 534 535 struct audio_info { 536 struct audio_info_flags flags; 537 uint32_t video_latency; 538 uint32_t audio_latency; 539 uint32_t display_index; 540 uint8_t display_name[AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS]; 541 uint32_t manufacture_id; 542 uint32_t product_id; 543 /* PortID used for ContainerID when defined */ 544 uint32_t port_id[2]; 545 uint32_t mode_count; 546 /* this field must be last in this struct */ 547 struct audio_mode modes[DC_MAX_AUDIO_DESC_COUNT]; 548 }; 549 struct audio_check { 550 unsigned int audio_packet_type; 551 unsigned int max_audiosample_rate; 552 unsigned int acat; 553 }; 554 enum dc_infoframe_type { 555 DC_HDMI_INFOFRAME_TYPE_VENDOR = 0x81, 556 DC_HDMI_INFOFRAME_TYPE_AVI = 0x82, 557 DC_HDMI_INFOFRAME_TYPE_SPD = 0x83, 558 DC_HDMI_INFOFRAME_TYPE_AUDIO = 0x84, 559 DC_DP_INFOFRAME_TYPE_PPS = 0x10, 560 }; 561 562 struct dc_info_packet { 563 bool valid; 564 uint8_t hb0; 565 uint8_t hb1; 566 uint8_t hb2; 567 uint8_t hb3; 568 uint8_t sb[32]; 569 }; 570 571 struct dc_info_packet_128 { 572 bool valid; 573 uint8_t hb0; 574 uint8_t hb1; 575 uint8_t hb2; 576 uint8_t hb3; 577 uint8_t sb[128]; 578 }; 579 580 #define DC_PLANE_UPDATE_TIMES_MAX 10 581 582 struct dc_plane_flip_time { 583 unsigned int time_elapsed_in_us[DC_PLANE_UPDATE_TIMES_MAX]; 584 unsigned int index; 585 unsigned int prev_update_time_in_us; 586 }; 587 588 enum dc_psr_state { 589 PSR_STATE0 = 0x0, 590 PSR_STATE1, 591 PSR_STATE1a, 592 PSR_STATE2, 593 PSR_STATE2a, 594 PSR_STATE2b, 595 PSR_STATE3, 596 PSR_STATE3Init, 597 PSR_STATE4, 598 PSR_STATE4a, 599 PSR_STATE4b, 600 PSR_STATE4c, 601 PSR_STATE4d, 602 PSR_STATE4_FULL_FRAME, 603 PSR_STATE4a_FULL_FRAME, 604 PSR_STATE4b_FULL_FRAME, 605 PSR_STATE4c_FULL_FRAME, 606 PSR_STATE4_FULL_FRAME_POWERUP, 607 PSR_STATE5, 608 PSR_STATE5a, 609 PSR_STATE5b, 610 PSR_STATE5c, 611 PSR_STATE_HWLOCK_MGR, 612 PSR_STATE_POLLVUPDATE, 613 PSR_STATE_INVALID = 0xFF 614 }; 615 616 struct psr_config { 617 unsigned char psr_version; 618 unsigned int psr_rfb_setup_time; 619 bool psr_exit_link_training_required; 620 bool psr_frame_capture_indication_req; 621 unsigned int psr_sdp_transmit_line_num_deadline; 622 bool allow_smu_optimizations; 623 bool allow_multi_disp_optimizations; 624 /* Panel self refresh 2 selective update granularity required */ 625 bool su_granularity_required; 626 /* psr2 selective update y granularity capability */ 627 uint8_t su_y_granularity; 628 unsigned int line_time_in_us; 629 uint8_t rate_control_caps; 630 uint16_t dsc_slice_height; 631 }; 632 633 union dmcu_psr_level { 634 struct { 635 unsigned int SKIP_CRC:1; 636 unsigned int SKIP_DP_VID_STREAM_DISABLE:1; 637 unsigned int SKIP_PHY_POWER_DOWN:1; 638 unsigned int SKIP_AUX_ACK_CHECK:1; 639 unsigned int SKIP_CRTC_DISABLE:1; 640 unsigned int SKIP_AUX_RFB_CAPTURE_CHECK:1; 641 unsigned int SKIP_SMU_NOTIFICATION:1; 642 unsigned int SKIP_AUTO_STATE_ADVANCE:1; 643 unsigned int DISABLE_PSR_ENTRY_ABORT:1; 644 unsigned int SKIP_SINGLE_OTG_DISABLE:1; 645 unsigned int DISABLE_ALPM:1; 646 unsigned int ALPM_DEFAULT_PD_MODE:1; 647 unsigned int RESERVED:20; 648 } bits; 649 unsigned int u32all; 650 }; 651 652 enum physical_phy_id { 653 PHYLD_0, 654 PHYLD_1, 655 PHYLD_2, 656 PHYLD_3, 657 PHYLD_4, 658 PHYLD_5, 659 PHYLD_6, 660 PHYLD_7, 661 PHYLD_8, 662 PHYLD_9, 663 PHYLD_COUNT, 664 PHYLD_UNKNOWN = (-1L) 665 }; 666 667 enum phy_type { 668 PHY_TYPE_UNKNOWN = 1, 669 PHY_TYPE_PCIE_PHY = 2, 670 PHY_TYPE_UNIPHY = 3, 671 }; 672 673 struct psr_context { 674 /* ddc line */ 675 enum channel_id channel; 676 /* Transmitter id */ 677 enum transmitter transmitterId; 678 /* Engine Id is used for Dig Be source select */ 679 enum engine_id engineId; 680 /* Controller Id used for Dig Fe source select */ 681 enum controller_id controllerId; 682 /* Pcie or Uniphy */ 683 enum phy_type phyType; 684 /* Physical PHY Id used by SMU interpretation */ 685 enum physical_phy_id smuPhyId; 686 /* Vertical total pixels from crtc timing. 687 * This is used for static screen detection. 688 * ie. If we want to detect half a frame, 689 * we use this to determine the hyst lines. 690 */ 691 unsigned int crtcTimingVerticalTotal; 692 /* PSR supported from panel capabilities and 693 * current display configuration 694 */ 695 bool psrSupportedDisplayConfig; 696 /* Whether fast link training is supported by the panel */ 697 bool psrExitLinkTrainingRequired; 698 /* If RFB setup time is greater than the total VBLANK time, 699 * it is not possible for the sink to capture the video frame 700 * in the same frame the SDP is sent. In this case, 701 * the frame capture indication bit should be set and an extra 702 * static frame should be transmitted to the sink. 703 */ 704 bool psrFrameCaptureIndicationReq; 705 /* Set the last possible line SDP may be transmitted without violating 706 * the RFB setup time or entering the active video frame. 707 */ 708 unsigned int sdpTransmitLineNumDeadline; 709 /* The VSync rate in Hz used to calculate the 710 * step size for smooth brightness feature 711 */ 712 unsigned int vsync_rate_hz; 713 unsigned int skipPsrWaitForPllLock; 714 unsigned int numberOfControllers; 715 /* Unused, for future use. To indicate that first changed frame from 716 * state3 shouldn't result in psr_inactive, but rather to perform 717 * an automatic single frame rfb_update. 718 */ 719 bool rfb_update_auto_en; 720 /* Number of frame before entering static screen */ 721 unsigned int timehyst_frames; 722 /* Partial frames before entering static screen */ 723 unsigned int hyst_lines; 724 /* # of repeated AUX transaction attempts to make before 725 * indicating failure to the driver 726 */ 727 unsigned int aux_repeats; 728 /* Controls hw blocks to power down during PSR active state */ 729 union dmcu_psr_level psr_level; 730 /* Controls additional delay after remote frame capture before 731 * continuing powerd own 732 */ 733 unsigned int frame_delay; 734 bool allow_smu_optimizations; 735 bool allow_multi_disp_optimizations; 736 /* Panel self refresh 2 selective update granularity required */ 737 bool su_granularity_required; 738 /* psr2 selective update y granularity capability */ 739 uint8_t su_y_granularity; 740 unsigned int line_time_in_us; 741 uint8_t rate_control_caps; 742 uint16_t dsc_slice_height; 743 }; 744 745 struct colorspace_transform { 746 struct fixed31_32 matrix[12]; 747 bool enable_remap; 748 }; 749 750 enum i2c_mot_mode { 751 I2C_MOT_UNDEF, 752 I2C_MOT_TRUE, 753 I2C_MOT_FALSE 754 }; 755 756 struct AsicStateEx { 757 unsigned int memoryClock; 758 unsigned int displayClock; 759 unsigned int engineClock; 760 unsigned int maxSupportedDppClock; 761 unsigned int dppClock; 762 unsigned int socClock; 763 unsigned int dcfClockDeepSleep; 764 unsigned int fClock; 765 unsigned int phyClock; 766 }; 767 768 769 enum dc_clock_type { 770 DC_CLOCK_TYPE_DISPCLK = 0, 771 DC_CLOCK_TYPE_DPPCLK = 1, 772 }; 773 774 struct dc_clock_config { 775 uint32_t max_clock_khz; 776 uint32_t min_clock_khz; 777 uint32_t bw_requirequired_clock_khz; 778 uint32_t current_clock_khz;/*current clock in use*/ 779 }; 780 781 struct hw_asic_id { 782 uint32_t chip_id; 783 uint32_t chip_family; 784 uint32_t pci_revision_id; 785 uint32_t hw_internal_rev; 786 uint32_t vram_type; 787 uint32_t vram_width; 788 uint32_t feature_flags; 789 uint32_t fake_paths_num; 790 void *atombios_base_address; 791 }; 792 793 struct dc_context { 794 struct dc *dc; 795 796 void *driver_context; /* e.g. amdgpu_device */ 797 struct dc_perf_trace *perf_trace; 798 void *cgs_device; 799 800 enum dce_environment dce_environment; 801 struct hw_asic_id asic_id; 802 803 /* todo: below should probably move to dc. to facilitate removal 804 * of AS we will store these here 805 */ 806 enum dce_version dce_version; 807 struct dc_bios *dc_bios; 808 bool created_bios; 809 struct gpio_service *gpio_service; 810 uint32_t dc_sink_id_count; 811 uint32_t dc_stream_id_count; 812 uint32_t dc_edp_id_count; 813 uint64_t fbc_gpu_addr; 814 struct dc_dmub_srv *dmub_srv; 815 #ifdef CONFIG_DRM_AMD_DC_HDCP 816 struct cp_psp cp_psp; 817 #endif 818 uint32_t *dcn_reg_offsets; 819 uint32_t *nbio_reg_offsets; 820 }; 821 822 /* DSC DPCD capabilities */ 823 union dsc_slice_caps1 { 824 struct { 825 uint8_t NUM_SLICES_1 : 1; 826 uint8_t NUM_SLICES_2 : 1; 827 uint8_t RESERVED : 1; 828 uint8_t NUM_SLICES_4 : 1; 829 uint8_t NUM_SLICES_6 : 1; 830 uint8_t NUM_SLICES_8 : 1; 831 uint8_t NUM_SLICES_10 : 1; 832 uint8_t NUM_SLICES_12 : 1; 833 } bits; 834 uint8_t raw; 835 }; 836 837 union dsc_slice_caps2 { 838 struct { 839 uint8_t NUM_SLICES_16 : 1; 840 uint8_t NUM_SLICES_20 : 1; 841 uint8_t NUM_SLICES_24 : 1; 842 uint8_t RESERVED : 5; 843 } bits; 844 uint8_t raw; 845 }; 846 847 union dsc_color_formats { 848 struct { 849 uint8_t RGB : 1; 850 uint8_t YCBCR_444 : 1; 851 uint8_t YCBCR_SIMPLE_422 : 1; 852 uint8_t YCBCR_NATIVE_422 : 1; 853 uint8_t YCBCR_NATIVE_420 : 1; 854 uint8_t RESERVED : 3; 855 } bits; 856 uint8_t raw; 857 }; 858 859 union dsc_color_depth { 860 struct { 861 uint8_t RESERVED1 : 1; 862 uint8_t COLOR_DEPTH_8_BPC : 1; 863 uint8_t COLOR_DEPTH_10_BPC : 1; 864 uint8_t COLOR_DEPTH_12_BPC : 1; 865 uint8_t RESERVED2 : 3; 866 } bits; 867 uint8_t raw; 868 }; 869 870 struct dsc_dec_dpcd_caps { 871 bool is_dsc_supported; 872 uint8_t dsc_version; 873 int32_t rc_buffer_size; /* DSC RC buffer block size in bytes */ 874 union dsc_slice_caps1 slice_caps1; 875 union dsc_slice_caps2 slice_caps2; 876 int32_t lb_bit_depth; 877 bool is_block_pred_supported; 878 int32_t edp_max_bits_per_pixel; /* Valid only in eDP */ 879 union dsc_color_formats color_formats; 880 union dsc_color_depth color_depth; 881 int32_t throughput_mode_0_mps; /* In MPs */ 882 int32_t throughput_mode_1_mps; /* In MPs */ 883 int32_t max_slice_width; 884 uint32_t bpp_increment_div; /* bpp increment divisor, e.g. if 16, it's 1/16th of a bit */ 885 886 /* Extended DSC caps */ 887 uint32_t branch_overall_throughput_0_mps; /* In MPs */ 888 uint32_t branch_overall_throughput_1_mps; /* In MPs */ 889 uint32_t branch_max_line_width; 890 bool is_dp; 891 }; 892 893 struct dc_golden_table { 894 uint16_t dc_golden_table_ver; 895 uint32_t aux_dphy_rx_control0_val; 896 uint32_t aux_dphy_tx_control_val; 897 uint32_t aux_dphy_rx_control1_val; 898 uint32_t dc_gpio_aux_ctrl_0_val; 899 uint32_t dc_gpio_aux_ctrl_1_val; 900 uint32_t dc_gpio_aux_ctrl_2_val; 901 uint32_t dc_gpio_aux_ctrl_3_val; 902 uint32_t dc_gpio_aux_ctrl_4_val; 903 uint32_t dc_gpio_aux_ctrl_5_val; 904 }; 905 906 enum dc_gpu_mem_alloc_type { 907 DC_MEM_ALLOC_TYPE_GART, 908 DC_MEM_ALLOC_TYPE_FRAME_BUFFER, 909 DC_MEM_ALLOC_TYPE_INVISIBLE_FRAME_BUFFER, 910 DC_MEM_ALLOC_TYPE_AGP 911 }; 912 913 enum dc_psr_version { 914 DC_PSR_VERSION_1 = 0, 915 DC_PSR_VERSION_SU_1 = 1, 916 DC_PSR_VERSION_UNSUPPORTED = 0xFFFFFFFF, 917 }; 918 919 /* Possible values of display_endpoint_id.endpoint */ 920 enum display_endpoint_type { 921 DISPLAY_ENDPOINT_PHY = 0, /* Physical connector. */ 922 DISPLAY_ENDPOINT_USB4_DPIA, /* USB4 DisplayPort tunnel. */ 923 DISPLAY_ENDPOINT_UNKNOWN = -1 924 }; 925 926 /* Extends graphics_object_id with an additional member 'ep_type' for 927 * distinguishing between physical endpoints (with entries in BIOS connector table) and 928 * logical endpoints. 929 */ 930 struct display_endpoint_id { 931 struct graphics_object_id link_id; 932 enum display_endpoint_type ep_type; 933 }; 934 935 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 936 struct otg_phy_mux { 937 uint8_t phy_output_num; 938 uint8_t otg_output_num; 939 }; 940 #endif 941 942 enum dc_detect_reason { 943 DETECT_REASON_BOOT, 944 DETECT_REASON_RESUMEFROMS3S4, 945 DETECT_REASON_HPD, 946 DETECT_REASON_HPDRX, 947 DETECT_REASON_FALLBACK, 948 DETECT_REASON_RETRAIN, 949 DETECT_REASON_TDR, 950 }; 951 952 struct dc_link_status { 953 bool link_active; 954 struct dpcd_caps *dpcd_caps; 955 }; 956 957 #if defined(CONFIG_DRM_AMD_DC_HDCP) 958 union hdcp_rx_caps { 959 struct { 960 uint8_t version; 961 uint8_t reserved; 962 struct { 963 uint8_t repeater : 1; 964 uint8_t hdcp_capable : 1; 965 uint8_t reserved : 6; 966 } byte0; 967 } fields; 968 uint8_t raw[3]; 969 }; 970 971 union hdcp_bcaps { 972 struct { 973 uint8_t HDCP_CAPABLE:1; 974 uint8_t REPEATER:1; 975 uint8_t RESERVED:6; 976 } bits; 977 uint8_t raw; 978 }; 979 980 struct hdcp_caps { 981 union hdcp_rx_caps rx_caps; 982 union hdcp_bcaps bcaps; 983 }; 984 #endif 985 #endif /* DC_TYPES_H_ */ 986