| /linux-6.3-rc2/drivers/gpu/drm/amd/amdgpu/ |
| A D | gfxhub_v1_0.c | 189 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); in gfxhub_v1_0_init_cache_regs()
190 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); in gfxhub_v1_0_init_cache_regs()
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| A D | amdgpu_gmc.h | 269 u64 VM_L2_CNTL2; member
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| A D | mmhub_v1_0.c | 175 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); in mmhub_v1_0_init_cache_regs()
176 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); in mmhub_v1_0_init_cache_regs()
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| A D | gfxhub_v2_1.c | 586 adev->gmc.VM_L2_CNTL2 = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL2); in gfxhub_v2_1_save_regs()
620 WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL2, adev->gmc.VM_L2_CNTL2); in gfxhub_v2_1_restore_regs()
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| A D | gmc_v7_0.c | 636 tmp = REG_SET_FIELD(0, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); in gmc_v7_0_gart_enable()
637 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); in gmc_v7_0_gart_enable()
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| A D | mmhub_v1_7.c | 195 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); in mmhub_v1_7_init_cache_regs()
196 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); in mmhub_v1_7_init_cache_regs()
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| A D | gmc_v8_0.c | 860 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); in gmc_v8_0_gart_enable()
861 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); in gmc_v8_0_gart_enable()
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| A D | sid.h | 379 #define VM_L2_CNTL2 0x501 macro
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| /linux-6.3-rc2/drivers/gpu/drm/radeon/ |
| A D | rv770.c | 921 WREG32(VM_L2_CNTL2, 0); in rv770_pcie_gart_enable()
967 WREG32(VM_L2_CNTL2, 0); in rv770_pcie_gart_disable()
998 WREG32(VM_L2_CNTL2, 0); in rv770_agp_enable()
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| A D | rv770d.h | 647 #define VM_L2_CNTL2 0x1404 macro
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| A D | nid.h | 117 #define VM_L2_CNTL2 0x1404 macro
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| A D | ni.c | 1287 WREG32(VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS | INVALIDATE_L2_CACHE); in cayman_pcie_gart_enable()
1366 WREG32(VM_L2_CNTL2, 0); in cayman_pcie_gart_disable()
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| A D | sid.h | 378 #define VM_L2_CNTL2 0x1404 macro
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| A D | cikd.h | 496 #define VM_L2_CNTL2 0x1404 macro
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| A D | evergreen.c | 2415 WREG32(VM_L2_CNTL2, 0); in evergreen_pcie_gart_enable()
2468 WREG32(VM_L2_CNTL2, 0); in evergreen_pcie_gart_disable()
2498 WREG32(VM_L2_CNTL2, 0); in evergreen_agp_enable()
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| A D | evergreend.h | 1155 #define VM_L2_CNTL2 0x1404 macro
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| A D | r600d.h | 592 #define VM_L2_CNTL2 0x1404 macro
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| A D | r600.c | 1145 WREG32(VM_L2_CNTL2, 0); in r600_pcie_gart_enable()
1237 WREG32(VM_L2_CNTL2, 0); in r600_agp_enable()
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| A D | si.c | 4306 WREG32(VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS | INVALIDATE_L2_CACHE); in si_pcie_gart_enable()
4392 WREG32(VM_L2_CNTL2, 0); in si_pcie_gart_disable()
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| A D | cik.c | 5445 WREG32(VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS | INVALIDATE_L2_CACHE); in cik_pcie_gart_enable()
5562 WREG32(VM_L2_CNTL2, 0); in cik_pcie_gart_disable()
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