| /linux-6.3-rc2/Documentation/devicetree/bindings/watchdog/ |
| A D | lpc18xx-wdt.txt | 1 * NXP LPC18xx Watchdog Timer (WDT)
5 - reg: Should contain WDT registers location and length
9 - interrupts: Should contain WDT interrupt
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| A D | imgpdc-wdt.txt | 1 *ImgTec PowerDown Controller (PDC) Watchdog Timer (WDT)
5 - reg : Should contain WDT registers location and length
9 - interrupts : Should contain WDT interrupt
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| A D | gpio-wdt.yaml | 18 description: GPIO connected to the WDT reset pin
25 Either a high-to-low or a low-to-high transition clears the WDT counter.
30 Low or high level starts counting WDT timeout, the opposite level
31 disables the WDT.
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| A D | xlnx,xps-timebase-wdt.yaml | 14 The Timebase watchdog timer(WDT) is a free-running 32 bit counter.
15 WDT uses a dual-expiration architecture. After one expiration of
16 the timeout interval, an interrupt is generated and the WDT state
19 expiration of the timeout interval, a WDT reset is generated.
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| A D | omap-wdt.txt | 1 TI Watchdog Timer (WDT) Controller for OMAP
5 - ti,hwmods : Name of the hwmod associated to the WDT
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| A D | davinci-wdt.txt | 1 Texas Instruments DaVinci/Keystone Watchdog Timer (WDT) Controller
5 - reg : Should contain WDT registers location and length
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| A D | realtek,otto-wdt.yaml | 17 - Phase 1: During this phase, the WDT can be pinged to reset the timeout.
20 During this phase, pinging the WDT has no effect, and a reset is
21 unavoidable, unless the WDT is disabled.
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| A D | qca-ar7130-wdt.txt | 1 * Qualcomm Atheros AR7130 Watchdog Timer (WDT) Controller
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| /linux-6.3-rc2/arch/sh/kernel/cpu/sh4/ |
| A D | setup-sh4-202.c | 89 HUDI, TMU0, TMU1, TMU2, RTC, SCIF, WDT, enumerator
100 INTC_VECT(WDT, 0x560),
105 { 0xffd00008, 0, 16, 4, /* IPRB */ { WDT, 0, 0, 0 } },
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| A D | setup-sh7750.c | 185 TMU3, TMU4, TMU0, TMU1, TMU2, RTC, SCI1, SCIF, WDT, REF, enumerator
201 INTC_VECT(WDT, 0x560),
207 { 0xffd00008, 0, 16, 4, /* IPRB */ { WDT, REF, SCI1, 0 } },
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| A D | setup-sh7760.c | 37 WDT, REF, enumerator
74 INTC_VECT(WDT, 0x560),
105 { 0xffd00008, 0, 16, 4, /* IPRB */ { WDT, REF, 0, 0 } },
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| /linux-6.3-rc2/arch/sh/kernel/cpu/sh3/ |
| A D | setup-sh7710.c | 28 RTC, WDT, REF, enumerator
53 INTC_VECT(WDT, 0x560),
59 { 0xfffffee4, 0, 16, 4, /* IPRB */ { WDT, REF, 0, 0 } },
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| A D | setup-sh7705.c | 31 RTC, WDT, REF_RCMI, enumerator
51 INTC_VECT(WDT, 0x560),
57 { 0xfffffee4, 0, 16, 4, /* IPRB */ { WDT, REF_RCMI, 0, 0 } },
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| A D | setup-sh770x.c | 32 RTC, WDT, REF, enumerator
42 INTC_VECT(WDT, 0x560),
69 { 0xfffffee4, 0, 16, 4, /* IPRB */ { WDT, REF, SCI, 0 } },
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| A D | setup-sh7720.c | 224 WDT, REF_RCMI, SIM, enumerator
243 INTC_VECT(WDT, 0x560), INTC_VECT(REF_RCMI, 0x580),
268 { 0xA414FEE4UL, 0, 16, 4, /* IPRB */ { WDT, REF_RCMI, SIM, 0 } },
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| /linux-6.3-rc2/arch/sh/kernel/cpu/sh2/ |
| A D | setup-sh7619.c | 22 WDT, EDMAC, CMT0, CMT1, enumerator
34 INTC_IRQ(WDT, 84), INTC_IRQ(EDMAC, 85),
51 { 0xf8080000, 0, 16, 4, /* IPRC */ { WDT, EDMAC, CMT0, CMT1 } },
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| /linux-6.3-rc2/Documentation/watchdog/ |
| A D | watchdog-parameters.rst | 29 Acquire WDT 'stop' io port (default 0x43)
31 Acquire WDT 'start' io port (default 0x443)
40 Advantech WDT 'stop' io port (default 0x443)
42 Advantech WDT 'start' io port (default 0x443)
179 Eurotech WDT io port (default=0x3f0)
181 Eurotech WDT irq (default=10)
183 Eurotech WDT event type (default is `int`)
391 pc87413 WDT I/O port (default: io).
484 SBC60xx WDT 'stop' io port (default 0x45)
486 SBC60xx WDT 'start' io port (default 0x443)
[all …]
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| A D | wdt.rst | 2 WDT Watchdog Timer Interfaces For The Linux Operating System
57 The external event interfaces on the WDT boards are not currently supported.
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| /linux-6.3-rc2/arch/sh/kernel/cpu/sh4a/ |
| A D | setup-sh7780.c | 304 RTC, WDT, TMU0, TMU1, TMU2, TMU2_TICPI, enumerator
317 INTC_VECT(WDT, 0x560),
360 HUDI, 0, WDT, SCIF1, SCIF0, RTC, TMU345, TMU012 } },
367 { 0xffd40008, 0, 32, 8, /* INT2PRI2 */ { SCIF0, SCIF1, WDT } },
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| A D | setup-sh7763.c | 240 RTC, WDT, TMU0, TMU1, TMU2, TMU2_TICPI, enumerator
256 INTC_VECT(WDT, 0x560), INTC_VECT(TMU0, 0x580),
306 HUDI, 0, WDT, SCIF1, SCIF0, RTC, TMU345, TMU012 } },
318 { 0xffd40008, 0, 32, 8, /* INT2PRI2 */ { SCIF0, SCIF1, WDT } },
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| A D | setup-sh7785.c | 377 WDT, TMU0, TMU1, TMU2, TMU2_TICPI, enumerator
393 INTC_VECT(WDT, 0x560),
455 PCIINTA, PCISERR, HAC1, HAC0, DMAC1, DMAC0, HUDI, WDT,
467 { 0xffd4000c, 0, 32, 8, /* INT2PRI3 */ { SCIF4, SCIF5, WDT, } },
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| /linux-6.3-rc2/arch/sh/kernel/cpu/sh2a/ |
| A D | setup-sh7206.c | 30 CMT0, CMT1, BSC, WDT, enumerator
61 INTC_IRQ(BSC, 148), INTC_IRQ(WDT, 152),
112 { 0xfffe0c04, 0, 16, 4, /* IPR08 */ { CMT0, CMT1, BSC, WDT } },
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| A D | setup-sh7203.c | 22 USB, LCDC, CMT0, CMT1, BSC, WDT, enumerator
63 INTC_IRQ(BSC, 144), INTC_IRQ(WDT, 145),
144 { 0xfffe0c06, 0, 16, 4, /* IPR09 */ { BSC, WDT, MTU0_ABCD, MTU0_VEF } },
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| A D | setup-sh7201.c | 28 RTC, WDT, enumerator
91 INTC_IRQ(WDT, 156),
159 { 0xfffe9806, 0, 16, 4, /* IPR09 */ { RTC, WDT, IIC30, 0 } },
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| /linux-6.3-rc2/Documentation/devicetree/bindings/power/reset/ |
| A D | keystone-reset.txt | 29 - ti,wdt-list: WDT list that can cause SoC reset. It's not related
30 to WDT driver, it's just needed to enable a SoC related
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