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Searched refs:WREG32_P (Results 1 – 25 of 69) sorted by relevance

123

/linux-6.3-rc2/drivers/gpu/drm/radeon/
A Duvd_v1_0.c227 WREG32_P(UVD_VCPU_CNTL, 0x10, ~0x10); in uvd_v1_0_init()
277 WREG32_P(UVD_MASTINT_EN, 0, ~(1 << 1)); in uvd_v1_0_start()
280 WREG32_P(UVD_LMI_CTRL2, 1 << 8, ~(1 << 8)); in uvd_v1_0_start()
281 WREG32_P(UVD_RB_ARB_CTRL, 1 << 3, ~(1 << 3)); in uvd_v1_0_start()
321 WREG32_P(UVD_LMI_CTRL2, 0, ~(1 << 8)); in uvd_v1_0_start()
323 WREG32_P(UVD_RB_ARB_CTRL, 0, ~(1 << 3)); in uvd_v1_0_start()
355 WREG32_P(UVD_MASTINT_EN, 3<<1, ~(3 << 1)); in uvd_v1_0_start()
397 WREG32_P(UVD_LMI_CTRL2, 1 << 8, ~(1 << 8)); in uvd_v1_0_stop()
398 WREG32_P(UVD_RB_ARB_CTRL, 1 << 3, ~(1 << 3)); in uvd_v1_0_stop()
409 WREG32_P(UVD_LMI_CTRL2, 0, ~(1 << 8)); in uvd_v1_0_stop()
[all …]
A Drs780_dpm.c260 WREG32_P(FVTHROT_PWM_CTRL_REG0, in rs780_voltage_scaling_init()
264 WREG32_P(FVTHROT_PWM_CTRL_REG0, in rs780_voltage_scaling_init()
287 WREG32_P(FVTHROT_PWM_FEEDBACK_DIV_REG1, in rs780_voltage_scaling_init()
309 WREG32_P(FVTHROT_CNTRL_REG, 0, in rs780_clk_scaling_enable()
338 WREG32_P(FVTHROT_FBDIV_REG2, in rs780_set_engine_clock_sc()
342 WREG32_P(FVTHROT_CNTRL_REG, in rs780_set_engine_clock_sc()
390 WREG32_P(FVTHROT_PWM_CTRL_REG0, in rs780_force_voltage()
394 WREG32_P(FVTHROT_PWM_CTRL_REG0, in rs780_force_voltage()
462 WREG32_P(FVTHROT_FBDIV_REG0, in rs780_set_engine_clock_scaling()
550 WREG32_P(FVTHROT_PWM_CTRL_REG0, in rs780_enable_voltage_scaling()
[all …]
A Dr600_dpm.c377 WREG32_P(CG_TPC, TPU(u), ~TPU_MASK); in r600_set_tpu()
382 WREG32_P(CG_TPC, TPCC(c), ~TPCC_MASK); in r600_set_tpc()
392 WREG32_P(CG_SSP, CG_SST(t), ~CG_SST_MASK); in r600_set_sst()
402 WREG32_P(CG_FC_T, FC_TU(u), ~FC_TU_MASK); in r600_set_fctu()
407 WREG32_P(CG_FC_T, FC_T(t), ~FC_T_MASK); in r600_set_fct()
422 WREG32_P(CG_VDDC3D_OOR, SU(u), ~SU_MASK); in r600_set_vddc3d_oorsu()
427 WREG32_P(CG_VDDC3D_OOR, PHC(p), ~PHC_MASK); in r600_set_vddc3d_oorphc()
508 WREG32_P(VID_RT, SSTU(u), ~SSTU_MASK); in r600_vid_rt_set_ssu()
579 WREG32_P(CTXSW_PROFILE_INDEX + (ix * 4), in r600_power_level_set_voltage_index()
588 WREG32_P(CTXSW_PROFILE_INDEX + (ix * 4), in r600_power_level_set_mem_clock_index()
[all …]
A Dvce_v1_0.c222 WREG32_P(VCE_CLOCK_GATING_A, 0, ~(1 << 16)); in vce_v1_0_resume()
224 WREG32_P(VCE_UENC_REG_CLOCK_GATING, 0x3F, ~0x3F); in vce_v1_0_resume()
227 WREG32_P(VCE_LMI_FW_PERIODIC_CTRL, 0x4, ~0x4); in vce_v1_0_resume()
230 WREG32_P(VCE_LMI_CACHE_CTRL, 0x0, ~0x1); in vce_v1_0_resume()
252 WREG32_P(VCE_LMI_CTRL2, 0x0, ~0x100); in vce_v1_0_resume()
295 WREG32_P(VCE_STATUS, 1, ~1); in vce_v1_0_start()
311 WREG32_P(VCE_VCPU_CNTL, VCE_CLK_EN, ~VCE_CLK_EN); in vce_v1_0_start()
313 WREG32_P(VCE_SOFT_RESET, in vce_v1_0_start()
321 WREG32_P(VCE_SOFT_RESET, 0, ~( in vce_v1_0_start()
340 WREG32_P(VCE_SOFT_RESET, 0, ~VCE_ECPU_SOFT_RESET); in vce_v1_0_start()
[all …]
A Dvce_v2_0.c163 WREG32_P(VCE_CLOCK_GATING_A, 0, ~(1 << 16)); in vce_v2_0_resume()
164 WREG32_P(VCE_UENC_CLOCK_GATING, 0x1FF000, ~0xFF9FF000); in vce_v2_0_resume()
165 WREG32_P(VCE_UENC_REG_CLOCK_GATING, 0x3F, ~0x3F); in vce_v2_0_resume()
169 WREG32_P(VCE_LMI_CACHE_CTRL, 0x0, ~0x1); in vce_v2_0_resume()
191 WREG32_P(VCE_LMI_CTRL2, 0x0, ~0x100); in vce_v2_0_resume()
193 WREG32_P(VCE_SYS_INT_EN, VCE_SYS_INT_TRAP_INTERRUPT_EN, in vce_v2_0_resume()
A Dr600_hdmi.c187 WREG32_P(acr_ctl + offset, in r600_hdmi_update_acr()
193 WREG32_P(HDMI0_ACR_32_0 + offset, in r600_hdmi_update_acr()
196 WREG32_P(HDMI0_ACR_32_1 + offset, in r600_hdmi_update_acr()
200 WREG32_P(HDMI0_ACR_44_0 + offset, in r600_hdmi_update_acr()
203 WREG32_P(HDMI0_ACR_44_1 + offset, in r600_hdmi_update_acr()
207 WREG32_P(HDMI0_ACR_48_0 + offset, in r600_hdmi_update_acr()
210 WREG32_P(HDMI0_ACR_48_1 + offset, in r600_hdmi_update_acr()
311 WREG32_P(HDMI0_AUDIO_PACKET_CONTROL + offset, in r600_hdmi_audio_workaround()
371 WREG32_P(HDMI0_INFOFRAME_CONTROL1 + offset, in r600_set_audio_packet()
384 WREG32_P(HDMI0_60958_0 + offset, in r600_set_audio_packet()
[all …]
A Dsumo_dpm.c128 WREG32_P(CG_GIT, CG_GICST(p), ~CG_GICST_MASK); in sumo_program_git()
175 WREG32_P(CG_PWR_GATING_CNTL, PGP(p) | PGU(u), in sumo_gfx_powergating_initialize()
181 WREG32_P(CG_CG_VOLTAGE_CNTL, PGP(p) | PGU(u), in sumo_gfx_powergating_initialize()
480 WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4), in sumo_set_divider_value()
483 WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4), in sumo_set_divider_value()
486 WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4), in sumo_set_divider_value()
489 WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4), in sumo_set_divider_value()
565 WREG32_P(DEEP_SLEEP_CNTL, 0, ~ENABLE_DS); in sumo_program_power_level()
906 WREG32_P(DEEP_SLEEP_CNTL, 0, ~ENABLE_DS); in sumo_enable_sclk_ds()
912 WREG32_P(CG_AT_0, CG_L(0), ~CG_L_MASK); in sumo_program_bootup_at()
[all …]
A Ddce3_1_afmt.c180 WREG32_P(HDMI0_ACR_32_0 + offset, in dce3_2_hdmi_update_acr()
183 WREG32_P(HDMI0_ACR_32_1 + offset, in dce3_2_hdmi_update_acr()
187 WREG32_P(HDMI0_ACR_44_0 + offset, in dce3_2_hdmi_update_acr()
190 WREG32_P(HDMI0_ACR_44_1 + offset, in dce3_2_hdmi_update_acr()
194 WREG32_P(HDMI0_ACR_48_0 + offset, in dce3_2_hdmi_update_acr()
197 WREG32_P(HDMI0_ACR_48_1 + offset, in dce3_2_hdmi_update_acr()
A Drv6xx_dpm.c317 WREG32_P(CG_SPLL_SPREAD_SPECTRUM_LOW + (index * 4), in rv6xx_set_engine_spread_spectrum_clk_s()
355 WREG32_P(CG_MPLL_SPREAD_SPECTRUM, SSEN, ~SSEN); in rv6xx_enable_memory_spread_spectrum()
357 WREG32_P(CG_MPLL_SPREAD_SPECTRUM, 0, ~SSEN); in rv6xx_enable_memory_spread_spectrum()
373 WREG32_P(MPLL_FREQ_LEVEL_0 + (index * 4), in rv6xx_memory_clock_entry_enable_post_divider()
382 WREG32_P(MPLL_FREQ_LEVEL_0 + (index * 4), in rv6xx_memory_clock_entry_set_post_divider()
396 WREG32_P(MPLL_FREQ_LEVEL_0 + (index * 4), in rv6xx_memory_clock_entry_set_reference_divider()
402 WREG32_P(VID_RT, BRT(rt), ~BRT_MASK); in rv6xx_vid_response_set_brt()
993 WREG32_P(MCLK_PWRMGT_CNTL, 0, ~USE_DISPLAY_GAP); in rv6xx_enable_display_gap()
1176 WREG32_P(GENERAL_PWRMGT, 0, in rv6xx_enable_backbias()
1239 WREG32_P(GENERAL_PWRMGT, 0, ~BACKBIAS_VALUE); in rv6xx_set_safe_backbias()
[all …]
A Drv770_dpm.c137 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN); in rv770_gfx_clock_gating_enable()
139 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~GFX_CLK_FORCE_ON); in rv770_gfx_clock_gating_enable()
183 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF); in rv770_start_dpm()
185 WREG32_P(MCLK_PWRMGT_CNTL, 0, ~MPLL_PWRMGT_OFF); in rv770_start_dpm()
199 WREG32_P(GENERAL_PWRMGT, 0, ~GLOBAL_PWRMGT_EN); in rv770_stop_dpm()
795 WREG32_P(CG_SPLL_SPREAD_SPECTRUM, 0, ~SSEN); in rv770_enable_spread_spectrum()
799 WREG32_P(CG_MPLL_SPREAD_SPECTRUM, 0, ~SSEN); in rv770_enable_spread_spectrum()
859 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_TREND_MODE); in rv770_program_tp()
1340 WREG32_P(GENERAL_PWRMGT, 0, ~VOLT_PWRMGT_EN); in rv770_enable_voltage_control()
1369 WREG32_P(GENERAL_PWRMGT, 0, ~ENABLE_GEN2PCIE); in rv770_enable_dynamic_pcie_gen2()
[all …]
A Dcypress_dpm.c93 WREG32_P(GENERAL_PWRMGT, 0, ~ENABLE_GEN2PCIE); in cypress_enable_dynamic_pcie_gen2()
102 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN);
104 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~GFX_CLK_FORCE_ON);
144 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN); in cypress_gfx_clock_gating_enable()
146 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~GFX_CLK_FORCE_ON); in cypress_gfx_clock_gating_enable()
229 WREG32_P(MPLL_CNTL_MODE, SS_SSEN, ~SS_SSEN); in cypress_enable_spread_spectrum()
231 WREG32_P(CG_SPLL_SPREAD_SPECTRUM, 0, ~SSEN); in cypress_enable_spread_spectrum()
233 WREG32_P(MPLL_CNTL_MODE, 0, ~SS_SSEN); in cypress_enable_spread_spectrum()
234 WREG32_P(MPLL_CNTL_MODE, 0, ~SS_DSMODE_EN); in cypress_enable_spread_spectrum()
247 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF); in cypress_enable_sclk_control()
[all …]
A Drv770_smc.c394 WREG32_P(SMC_IO, SMC_RST_N, ~SMC_RST_N); in rv770_start_smc()
399 WREG32_P(SMC_IO, 0, ~SMC_RST_N); in rv770_reset_smc()
404 WREG32_P(SMC_IO, 0, ~SMC_CLK_EN); in rv770_stop_smc_clock()
409 WREG32_P(SMC_IO, SMC_CLK_EN, ~SMC_CLK_EN); in rv770_start_smc_clock()
433 WREG32_P(SMC_MSG, HOST_SMC_MSG(msg), ~HOST_SMC_MSG_MASK); in rv770_send_msg_to_smc()
A Dci_smc.c42 WREG32_P(SMC_IND_ACCESS_CNTL, 0, ~AUTO_INCREMENT_IND_0); in ci_set_smc_sram_address()
230 WREG32_P(SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, ~AUTO_INCREMENT_IND_0); in ci_load_smc_ucode()
240 WREG32_P(SMC_IND_ACCESS_CNTL, 0, ~AUTO_INCREMENT_IND_0); in ci_load_smc_ucode()
A Drv770.c64 WREG32_P(CG_UPLL_FUNC_CNTL_2, in rv770_set_uvd_clocks()
70 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_SLEEP_MASK, ~UPLL_SLEEP_MASK); in rv770_set_uvd_clocks()
92 WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(1), ~UPLL_FB_DIV(1)); in rv770_set_uvd_clocks()
99 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_RESET_MASK, ~UPLL_RESET_MASK); in rv770_set_uvd_clocks()
102 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_REF_DIV(1), ~UPLL_REF_DIV_MASK); in rv770_set_uvd_clocks()
103 WREG32_P(CG_UPLL_FUNC_CNTL_2, in rv770_set_uvd_clocks()
110 WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(fb_div), in rv770_set_uvd_clocks()
117 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK); in rv770_set_uvd_clocks()
122 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_BYPASS_EN_MASK); in rv770_set_uvd_clocks()
123 WREG32_P(CG_UPLL_FUNC_CNTL_3, 0, ~UPLL_FB_DIV(1)); in rv770_set_uvd_clocks()
[all …]
A Dradeon_legacy_crtc.c331 WREG32_P(RADEON_CRTC2_GEN_CNTL, RADEON_CRTC2_EN, ~(RADEON_CRTC2_EN | mask)); in radeon_crtc_dpms()
333 WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_EN, ~(RADEON_CRTC_EN | in radeon_crtc_dpms()
335 WREG32_P(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl, ~(mask | crtc_ext_cntl)); in radeon_crtc_dpms()
347 WREG32_P(RADEON_CRTC2_GEN_CNTL, mask, ~(RADEON_CRTC2_EN | mask)); in radeon_crtc_dpms()
349 WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_DISP_REQ_EN_B, ~(RADEON_CRTC_EN | in radeon_crtc_dpms()
351 WREG32_P(RADEON_CRTC_EXT_CNTL, mask, ~(mask | crtc_ext_cntl)); in radeon_crtc_dpms()
937 WREG32_P(RADEON_CLOCK_CNTL_INDEX, in radeon_set_pll()
958 WREG32_P(RADEON_CLOCK_CNTL_INDEX, in radeon_set_pll()
/linux-6.3-rc2/drivers/gpu/drm/amd/amdgpu/
A Duvd_v3_1.c331 WREG32_P(mmUVD_STATUS, 1<<2, ~(1<<2)); in uvd_v3_1_start()
344 WREG32_P(mmUVD_MASTINT_EN, 0, ~(1 << 1)); in uvd_v3_1_start()
372 WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8)); in uvd_v3_1_start()
395 WREG32_P(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK, in uvd_v3_1_start()
409 WREG32_P(mmUVD_MASTINT_EN, 3<<1, ~(3 << 1)); in uvd_v3_1_start()
411 WREG32_P(mmUVD_STATUS, 0, ~(1<<2)); in uvd_v3_1_start()
435 WREG32_P(mmUVD_RBC_RB_CNTL, rb_bufsz, ~0x11f1f); in uvd_v3_1_start()
477 WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8)); in uvd_v3_1_stop()
490 WREG32_P(0x3D49, 0, ~(1 << 2)); in uvd_v3_1_stop()
492 WREG32_P(mmUVD_VCPU_CNTL, 0, ~(1 << 9)); in uvd_v3_1_stop()
[all …]
A Duvd_v4_2.c289 WREG32_P(mmUVD_STATUS, 1<<2, ~(1<<2)); in uvd_v4_2_start()
302 WREG32_P(mmUVD_MASTINT_EN, 0, ~(1 << 1)); in uvd_v4_2_start()
330 WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8)); in uvd_v4_2_start()
353 WREG32_P(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK, in uvd_v4_2_start()
367 WREG32_P(mmUVD_MASTINT_EN, 3<<1, ~(3 << 1)); in uvd_v4_2_start()
369 WREG32_P(mmUVD_STATUS, 0, ~(1<<2)); in uvd_v4_2_start()
393 WREG32_P(mmUVD_RBC_RB_CNTL, rb_bufsz, ~0x11f1f); in uvd_v4_2_start()
435 WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8)); in uvd_v4_2_stop()
448 WREG32_P(0x3D49, 0, ~(1 << 2)); in uvd_v4_2_stop()
450 WREG32_P(mmUVD_VCPU_CNTL, 0, ~(1 << 9)); in uvd_v4_2_stop()
[all …]
A Dvce_v2_0.c130 WREG32_P(mmVCE_SOFT_RESET, in vce_v2_0_firmware_loaded()
134 WREG32_P(mmVCE_SOFT_RESET, 0, in vce_v2_0_firmware_loaded()
172 WREG32_P(mmVCE_CLOCK_GATING_A, 0, ~(1 << 16)); in vce_v2_0_mc_resume()
174 WREG32_P(mmVCE_UENC_REG_CLOCK_GATING, 0x3F, ~0x3F); in vce_v2_0_mc_resume()
178 WREG32_P(mmVCE_LMI_CACHE_CTRL, 0x0, ~0x1); in vce_v2_0_mc_resume()
200 WREG32_P(mmVCE_LMI_CTRL2, 0x0, ~0x100); in vce_v2_0_mc_resume()
236 WREG32_P(mmVCE_STATUS, 1, ~1); in vce_v2_0_start()
265 WREG32_P(mmVCE_STATUS, 0, ~1); in vce_v2_0_start()
291 WREG32_P(mmVCE_LMI_CTRL2, 1 << 8, ~(1 << 8)); in vce_v2_0_stop()
300 WREG32_P(mmVCE_VCPU_CNTL, 0, ~0x80001); in vce_v2_0_stop()
[all …]
A Duvd_v5_0.c324 WREG32_P(mmUVD_POWER_STATUS, 0, ~(1 << 2)); in uvd_v5_0_start()
333 WREG32_P(mmUVD_MASTINT_EN, 0, ~(1 << 1)); in uvd_v5_0_start()
336 WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8)); in uvd_v5_0_start()
378 WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8)); in uvd_v5_0_start()
397 WREG32_P(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK, in uvd_v5_0_start()
410 WREG32_P(mmUVD_MASTINT_EN, 3 << 1, ~(3 << 1)); in uvd_v5_0_start()
413 WREG32_P(mmUVD_STATUS, 0, ~(2 << 1)); in uvd_v5_0_start()
444 WREG32_P(mmUVD_RBC_RB_CNTL, 0, ~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK); in uvd_v5_0_start()
462 WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8)); in uvd_v5_0_stop()
473 WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8)); in uvd_v5_0_stop()
[all …]
A Dvce_v4_0.c140 WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_SOFT_RESET), in vce_v4_0_firmware_loaded()
144 WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_SOFT_RESET), 0, in vce_v4_0_firmware_loaded()
369 WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CNTL), 1, ~0x200001); in vce_v4_0_start()
371 WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_SOFT_RESET), 0, in vce_v4_0_start()
392 WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CNTL), 0, ~0x200001); in vce_v4_0_stop()
395 WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_SOFT_RESET), in vce_v4_0_stop()
639 WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_CLOCK_GATING_A), 0, ~(1 << 16)); in vce_v4_0_mc_resume()
645 WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_CACHE_CTRL), 0x0, ~0x1); in vce_v4_0_mc_resume()
685 WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_CTRL2), 0x0, ~0x100); in vce_v4_0_mc_resume()
686 WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_SYS_INT_EN), in vce_v4_0_mc_resume()
[all …]
A Djpeg_v3_0.c285 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_POWER_STATUS), 0, in jpeg_v3_0_disable_static_power_gating()
289 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_POWER_STATUS), 0, in jpeg_v3_0_disable_static_power_gating()
298 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_POWER_STATUS), in jpeg_v3_0_enable_static_power_gating()
352 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JMI_CNTL), 0, in jpeg_v3_0_start()
356 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmJPEG_SYS_INT_EN), in jpeg_v3_0_start()
387 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JMI_CNTL), in jpeg_v3_0_stop()
A Djpeg_v4_0.c300 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regUVD_JPEG_POWER_STATUS), 0, in jpeg_v4_0_disable_static_power_gating()
304 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regUVD_JPEG_POWER_STATUS), 0, in jpeg_v4_0_disable_static_power_gating()
313 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regUVD_JPEG_POWER_STATUS), in jpeg_v4_0_enable_static_power_gating()
366 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regUVD_JMI_CNTL), 0, in jpeg_v4_0_start()
370 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regJPEG_SYS_INT_EN), in jpeg_v4_0_start()
401 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regUVD_JMI_CNTL), in jpeg_v4_0_stop()
A Dsi.c1644 WREG32_P(cg_upll_func_cntl, 0, ~UPLL_CTLREQ_MASK); in si_uvd_send_upll_ctlreq()
1661 WREG32_P(cg_upll_func_cntl, 0, ~UPLL_CTLREQ_MASK); in si_uvd_send_upll_ctlreq()
1781 WREG32_P(CG_UPLL_FUNC_CNTL_2, in si_set_uvd_clocks()
1806 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_SLEEP_MASK); in si_set_uvd_clocks()
1809 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK); in si_set_uvd_clocks()
1821 WREG32_P(CG_UPLL_SPREAD_SPECTRUM, 0, ~SSEN_MASK); in si_set_uvd_clocks()
1827 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_REF_DIV_MASK); in si_set_uvd_clocks()
1832 WREG32_P(CG_UPLL_FUNC_CNTL_4, in si_set_uvd_clocks()
1837 WREG32_P(CG_UPLL_FUNC_CNTL_2, in si_set_uvd_clocks()
1845 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK); in si_set_uvd_clocks()
[all …]
A Dvcn_v2_5.c983 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), in vcn_v2_5_start()
987 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_MASTINT_EN), 0, in vcn_v2_5_start()
1039 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_LMI_CTRL2), 0, in vcn_v2_5_start()
1046 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0, in vcn_v2_5_start()
1066 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), in vcn_v2_5_start()
1083 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_MASTINT_EN), in vcn_v2_5_start()
1088 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_STATUS), 0, in vcn_v2_5_start()
1402 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_RB_ARB_CTRL), in vcn_v2_5_stop()
1407 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), in vcn_v2_5_stop()
1412 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0, in vcn_v2_5_stop()
[all …]
/linux-6.3-rc2/drivers/gpu/drm/amd/pm/legacy-dpm/
A Dsi_smc.c42 WREG32_P(SMC_IND_ACCESS_CNTL, 0, ~AUTO_INCREMENT_IND_0); in si_set_smc_sram_address()
229 WREG32_P(SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, ~AUTO_INCREMENT_IND_0); in amdgpu_si_load_smc_ucode()
239 WREG32_P(SMC_IND_ACCESS_CNTL, 0, ~AUTO_INCREMENT_IND_0); in amdgpu_si_load_smc_ucode()

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