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Searched refs:WREG32_SOC15_IP (Results 1 – 12 of 12) sorted by relevance

/linux-6.3-rc2/drivers/gpu/drm/amd/amdgpu/
A Dsdma_v6_0.c213 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, in sdma_v6_0_ring_set_wptr()
216 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, in sdma_v6_0_ring_set_wptr()
441 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL), f32_cntl); in sdma_v6_0_enable()
483 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR), 0); in sdma_v6_0_gfx_resume()
485 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR), 0); in sdma_v6_0_gfx_resume()
549 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UTCL1_CNTL), temp); in sdma_v6_0_gfx_resume()
558 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UTCL1_PAGE), temp); in sdma_v6_0_gfx_resume()
565 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL), temp); in sdma_v6_0_gfx_resume()
726 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_FREEZE), tmp); in sdma_v6_0_soft_reset()
730 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL), tmp); in sdma_v6_0_soft_reset()
[all …]
A Dsdma_v5_2.c430 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE0_QUANTUM), in sdma_v5_2_ctx_switch_enable()
432 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE1_QUANTUM), in sdma_v5_2_ctx_switch_enable()
434 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE2_QUANTUM), in sdma_v5_2_ctx_switch_enable()
513 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), 0); in sdma_v5_2_gfx_resume()
514 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), 0); in sdma_v5_2_gfx_resume()
515 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), 0); in sdma_v5_2_gfx_resume()
516 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), 0); in sdma_v5_2_gfx_resume()
533 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_HI), in sdma_v5_2_gfx_resume()
535 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_LO), in sdma_v5_2_gfx_resume()
591 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL), temp); in sdma_v5_2_gfx_resume()
[all …]
A Dsdma_v5_0.c391 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, in sdma_v5_0_ring_set_wptr()
394 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, in sdma_v5_0_ring_set_wptr()
633 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE0_QUANTUM), in sdma_v5_0_ctx_switch_enable()
635 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE1_QUANTUM), in sdma_v5_0_ctx_switch_enable()
637 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE2_QUANTUM), in sdma_v5_0_ctx_switch_enable()
712 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), 0); in sdma_v5_0_gfx_resume()
713 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), 0); in sdma_v5_0_gfx_resume()
714 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), 0); in sdma_v5_0_gfx_resume()
715 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), 0); in sdma_v5_0_gfx_resume()
739 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE), in sdma_v5_0_gfx_resume()
[all …]
A Damdgpu_gmc.c623 WREG32_SOC15_IP(GC, reg, tmp) : in amdgpu_gmc_set_vm_fault_masks()
624 WREG32_SOC15_IP(MMHUB, reg, tmp); in amdgpu_gmc_set_vm_fault_masks()
A Dgmc_v9_0.c503 WREG32_SOC15_IP(GC, reg, tmp); in gmc_v9_0_vm_fault_interrupt_state()
505 WREG32_SOC15_IP(MMHUB, reg, tmp); in gmc_v9_0_vm_fault_interrupt_state()
531 WREG32_SOC15_IP(GC, reg, tmp); in gmc_v9_0_vm_fault_interrupt_state()
533 WREG32_SOC15_IP(MMHUB, reg, tmp); in gmc_v9_0_vm_fault_interrupt_state()
A Dsoc15_common.h75 #define WREG32_SOC15_IP(ip, reg, value) \ macro
A Damdgpu_amdkfd_gfx_v10.c225 WREG32_SOC15_IP(GC, reg, mqd_hqd[reg - hqd_base]); in kgd_hqd_load()
A Damdgpu_amdkfd_gfx_v10_3.c212 WREG32_SOC15_IP(GC, reg, mqd_hqd[reg - hqd_base]); in hqd_load_v10_3()
A Dgfx_v11_0.c5800 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); in gfx_v11_0_set_gfx_eop_interrupt_state()
5808 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); in gfx_v11_0_set_gfx_eop_interrupt_state()
5857 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); in gfx_v11_0_set_compute_eop_interrupt_state()
5865 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); in gfx_v11_0_set_compute_eop_interrupt_state()
5877 WREG32_SOC15_IP(GC, reg_addr, tmp); \
6111 WREG32_SOC15_IP(GC, target, tmp);
6121 WREG32_SOC15_IP(GC, target, tmp);
A Dsoc15.c497 WREG32_SOC15_IP(GC, reg, tmp) : WREG32(reg, tmp); in soc15_program_register_sequence()
A Dgfx_v10_0.c8899 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); in gfx_v10_0_set_gfx_eop_interrupt_state()
8905 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); in gfx_v10_0_set_gfx_eop_interrupt_state()
8952 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); in gfx_v10_0_set_compute_eop_interrupt_state()
8958 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); in gfx_v10_0_set_compute_eop_interrupt_state()
9177 WREG32_SOC15_IP(GC, target, tmp); in gfx_v10_0_kiq_set_interrupt_state()
9187 WREG32_SOC15_IP(GC, target, tmp); in gfx_v10_0_kiq_set_interrupt_state()
A Dgfx_v9_0.c5647 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); in gfx_v9_0_set_compute_eop_interrupt_state()
5653 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); in gfx_v9_0_set_compute_eop_interrupt_state()

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