Searched refs:WR_CONFIRM (Results 1 – 11 of 11) sorted by relevance
119 #define WR_CONFIRM (1 << 20) macro
98 #define WR_CONFIRM (1 << 20) macro
151 #define WR_CONFIRM (1 << 20) macro
269 #define WR_CONFIRM (1 << 20) macro
964 (wc ? WR_CONFIRM : 0)); in gfx_v9_0_write_data_to_reg()1046 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; in gfx_v9_0_ring_test_ib()5279 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); in gfx_v9_0_ring_emit_fence_kiq()5288 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); in gfx_v9_0_ring_emit_fence_kiq()5328 WR_CONFIRM) | in gfx_v9_0_ring_emit_ce_meta()5437 WR_CONFIRM) | in gfx_v9_0_ring_emit_de_meta()5541 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM; in gfx_v9_0_ring_emit_wreg()5547 cmd = WR_CONFIRM; in gfx_v9_0_ring_emit_wreg()
892 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; in gfx_v8_0_ring_test_ib()6275 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); in gfx_v8_0_ring_emit_fence_kiq()6284 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); in gfx_v8_0_ring_emit_fence_kiq()6381 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM; in gfx_v8_0_ring_emit_wreg()6387 cmd = WR_CONFIRM; in gfx_v8_0_ring_emit_wreg()7192 WR_CONFIRM) | in gfx_v8_0_ring_emit_ce_meta()7225 WR_CONFIRM) | in gfx_v8_0_ring_emit_de_meta()
285 WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0)); in gfx_v11_0_write_data_to_reg()401 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; in gfx_v11_0_ring_test_ib()5530 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); in gfx_v11_0_ring_emit_fence_kiq()5539 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); in gfx_v11_0_ring_emit_fence_kiq()5678 WR_CONFIRM) | in gfx_v11_0_ring_emit_de_meta()5724 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM; in gfx_v11_0_ring_emit_wreg()5730 cmd = WR_CONFIRM; in gfx_v11_0_ring_emit_wreg()
3752 WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0)); in gfx_v10_0_write_data_to_reg()3860 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; in gfx_v10_0_ring_test_ib()8563 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); in gfx_v10_0_ring_emit_fence_kiq()8572 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); in gfx_v10_0_ring_emit_fence_kiq()8720 WR_CONFIRM) | in gfx_v10_0_ring_emit_ce_meta()8771 WR_CONFIRM) | in gfx_v10_0_ring_emit_de_meta()8817 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM; in gfx_v10_0_ring_emit_wreg()8823 cmd = WR_CONFIRM; in gfx_v10_0_ring_emit_wreg()
1709 #define WR_CONFIRM (1 << 20) macro
1646 #define WR_CONFIRM (1 << 20) macro
1737 #define WR_CONFIRM (1 << 20) macro
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