1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3  * Copyright (C) 2017-2020 Xilinx, Inc. All rights reserved.
4  * Copyright (C) 2022, Advanced Micro Devices, Inc.
5  */
6 
7 #ifndef __DMA_XDMA_REGS_H
8 #define __DMA_XDMA_REGS_H
9 
10 /* The length of register space exposed to host */
11 #define XDMA_REG_SPACE_LEN	65536
12 
13 /*
14  * maximum number of DMA channels for each direction:
15  * Host to Card (H2C) or Card to Host (C2H)
16  */
17 #define XDMA_MAX_CHANNELS	4
18 
19 /*
20  * macros to define the number of descriptor blocks can be used in one
21  * DMA transfer request.
22  * the DMA engine uses a linked list of descriptor blocks that specify the
23  * source, destination, and length of the DMA transfers.
24  */
25 #define XDMA_DESC_BLOCK_NUM		BIT(7)
26 #define XDMA_DESC_BLOCK_MASK		(XDMA_DESC_BLOCK_NUM - 1)
27 
28 /* descriptor definitions */
29 #define XDMA_DESC_ADJACENT		32
30 #define XDMA_DESC_ADJACENT_MASK		(XDMA_DESC_ADJACENT - 1)
31 #define XDMA_DESC_ADJACENT_BITS		GENMASK(13, 8)
32 #define XDMA_DESC_MAGIC			0xad4bUL
33 #define XDMA_DESC_MAGIC_BITS		GENMASK(31, 16)
34 #define XDMA_DESC_FLAGS_BITS		GENMASK(7, 0)
35 #define XDMA_DESC_STOPPED		BIT(0)
36 #define XDMA_DESC_COMPLETED		BIT(1)
37 #define XDMA_DESC_BLEN_BITS		28
38 #define XDMA_DESC_BLEN_MAX		(BIT(XDMA_DESC_BLEN_BITS) - PAGE_SIZE)
39 
40 /* macros to construct the descriptor control word */
41 #define XDMA_DESC_CONTROL(adjacent, flag)				\
42 	(FIELD_PREP(XDMA_DESC_MAGIC_BITS, XDMA_DESC_MAGIC) |		\
43 	 FIELD_PREP(XDMA_DESC_ADJACENT_BITS, (adjacent) - 1) |		\
44 	 FIELD_PREP(XDMA_DESC_FLAGS_BITS, (flag)))
45 #define XDMA_DESC_CONTROL_LAST						\
46 	XDMA_DESC_CONTROL(1, XDMA_DESC_STOPPED | XDMA_DESC_COMPLETED)
47 
48 /*
49  * Descriptor for a single contiguous memory block transfer.
50  *
51  * Multiple descriptors are linked by means of the next pointer. An additional
52  * extra adjacent number gives the amount of extra contiguous descriptors.
53  *
54  * The descriptors are in root complex memory, and the bytes in the 32-bit
55  * words must be in little-endian byte ordering.
56  */
57 struct xdma_hw_desc {
58 	__le32		control;
59 	__le32		bytes;
60 	__le64		src_addr;
61 	__le64		dst_addr;
62 	__le64		next_desc;
63 };
64 
65 #define XDMA_DESC_SIZE		sizeof(struct xdma_hw_desc)
66 #define XDMA_DESC_BLOCK_SIZE	(XDMA_DESC_SIZE * XDMA_DESC_ADJACENT)
67 #define XDMA_DESC_BLOCK_ALIGN	4096
68 
69 /*
70  * Channel registers
71  */
72 #define XDMA_CHAN_IDENTIFIER		0x0
73 #define XDMA_CHAN_CONTROL		0x4
74 #define XDMA_CHAN_CONTROL_W1S		0x8
75 #define XDMA_CHAN_CONTROL_W1C		0xc
76 #define XDMA_CHAN_STATUS		0x40
77 #define XDMA_CHAN_COMPLETED_DESC	0x48
78 #define XDMA_CHAN_ALIGNMENTS		0x4c
79 #define XDMA_CHAN_INTR_ENABLE		0x90
80 #define XDMA_CHAN_INTR_ENABLE_W1S	0x94
81 #define XDMA_CHAN_INTR_ENABLE_W1C	0x9c
82 
83 #define XDMA_CHAN_STRIDE	0x100
84 #define XDMA_CHAN_H2C_OFFSET	0x0
85 #define XDMA_CHAN_C2H_OFFSET	0x1000
86 #define XDMA_CHAN_H2C_TARGET	0x0
87 #define XDMA_CHAN_C2H_TARGET	0x1
88 
89 /* macro to check if channel is available */
90 #define XDMA_CHAN_MAGIC		0x1fc0
91 #define XDMA_CHAN_CHECK_TARGET(id, target)		\
92 	(((u32)(id) >> 16) == XDMA_CHAN_MAGIC + (target))
93 
94 /* bits of the channel control register */
95 #define CHAN_CTRL_RUN_STOP			BIT(0)
96 #define CHAN_CTRL_IE_DESC_STOPPED		BIT(1)
97 #define CHAN_CTRL_IE_DESC_COMPLETED		BIT(2)
98 #define CHAN_CTRL_IE_DESC_ALIGN_MISMATCH	BIT(3)
99 #define CHAN_CTRL_IE_MAGIC_STOPPED		BIT(4)
100 #define CHAN_CTRL_IE_IDLE_STOPPED		BIT(6)
101 #define CHAN_CTRL_IE_READ_ERROR			GENMASK(13, 9)
102 #define CHAN_CTRL_IE_DESC_ERROR			GENMASK(23, 19)
103 #define CHAN_CTRL_NON_INCR_ADDR			BIT(25)
104 #define CHAN_CTRL_POLL_MODE_WB			BIT(26)
105 
106 #define CHAN_CTRL_START	(CHAN_CTRL_RUN_STOP |				\
107 			 CHAN_CTRL_IE_DESC_STOPPED |			\
108 			 CHAN_CTRL_IE_DESC_COMPLETED |			\
109 			 CHAN_CTRL_IE_DESC_ALIGN_MISMATCH |		\
110 			 CHAN_CTRL_IE_MAGIC_STOPPED |			\
111 			 CHAN_CTRL_IE_READ_ERROR |			\
112 			 CHAN_CTRL_IE_DESC_ERROR)
113 
114 /* bits of the channel interrupt enable mask */
115 #define CHAN_IM_DESC_ERROR			BIT(19)
116 #define CHAN_IM_READ_ERROR			BIT(9)
117 #define CHAN_IM_IDLE_STOPPED			BIT(6)
118 #define CHAN_IM_MAGIC_STOPPED			BIT(4)
119 #define CHAN_IM_DESC_COMPLETED			BIT(2)
120 #define CHAN_IM_DESC_STOPPED			BIT(1)
121 
122 #define CHAN_IM_ALL	(CHAN_IM_DESC_ERROR | CHAN_IM_READ_ERROR |	\
123 			 CHAN_IM_IDLE_STOPPED | CHAN_IM_MAGIC_STOPPED | \
124 			 CHAN_IM_DESC_COMPLETED | CHAN_IM_DESC_STOPPED)
125 
126 /*
127  * Channel SGDMA registers
128  */
129 #define XDMA_SGDMA_IDENTIFIER	0x4000
130 #define XDMA_SGDMA_DESC_LO	0x4080
131 #define XDMA_SGDMA_DESC_HI	0x4084
132 #define XDMA_SGDMA_DESC_ADJ	0x4088
133 #define XDMA_SGDMA_DESC_CREDIT	0x408c
134 
135 /* bits of the SG DMA control register */
136 #define XDMA_CTRL_RUN_STOP			BIT(0)
137 #define XDMA_CTRL_IE_DESC_STOPPED		BIT(1)
138 #define XDMA_CTRL_IE_DESC_COMPLETED		BIT(2)
139 #define XDMA_CTRL_IE_DESC_ALIGN_MISMATCH	BIT(3)
140 #define XDMA_CTRL_IE_MAGIC_STOPPED		BIT(4)
141 #define XDMA_CTRL_IE_IDLE_STOPPED		BIT(6)
142 #define XDMA_CTRL_IE_READ_ERROR			GENMASK(13, 9)
143 #define XDMA_CTRL_IE_DESC_ERROR			GENMASK(23, 19)
144 #define XDMA_CTRL_NON_INCR_ADDR			BIT(25)
145 #define XDMA_CTRL_POLL_MODE_WB			BIT(26)
146 
147 /*
148  * interrupt registers
149  */
150 #define XDMA_IRQ_IDENTIFIER		0x2000
151 #define XDMA_IRQ_USER_INT_EN		0x2004
152 #define XDMA_IRQ_USER_INT_EN_W1S	0x2008
153 #define XDMA_IRQ_USER_INT_EN_W1C	0x200c
154 #define XDMA_IRQ_CHAN_INT_EN		0x2010
155 #define XDMA_IRQ_CHAN_INT_EN_W1S	0x2014
156 #define XDMA_IRQ_CHAN_INT_EN_W1C	0x2018
157 #define XDMA_IRQ_USER_INT_REQ		0x2040
158 #define XDMA_IRQ_CHAN_INT_REQ		0x2044
159 #define XDMA_IRQ_USER_INT_PEND		0x2048
160 #define XDMA_IRQ_CHAN_INT_PEND		0x204c
161 #define XDMA_IRQ_USER_VEC_NUM		0x2080
162 #define XDMA_IRQ_CHAN_VEC_NUM		0x20a0
163 
164 #define XDMA_IRQ_VEC_SHIFT		8
165 
166 #endif /* __DMA_XDMA_REGS_H */
167