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Searched refs:_MASKED_BIT_ENABLE (Results 1 – 21 of 21) sorted by relevance

/linux-6.3-rc2/drivers/gpu/drm/i915/gvt/
A Dreg.h97 (((_val) & _MASKED_BIT_ENABLE(_b)) == _MASKED_BIT_ENABLE(_b))
A Dmmio_context.c466 _MASKED_BIT_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT); in is_inhibit_context()
A Dhandlers.c2016 (*(u32 *)p_data) &= ~_MASKED_BIT_ENABLE(1); in ring_mode_mmio_write()
2019 (*(u32 *)p_data) &= ~_MASKED_BIT_ENABLE(2); in ring_mode_mmio_write()
2121 (*(u32 *)p_data) &= ~_MASKED_BIT_ENABLE(0x18); in csfe_chicken1_mmio_write()
2498 ~_MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET), D_BDW_PLUS, NULL, in init_bdw_mmio_info()
/linux-6.3-rc2/drivers/gpu/drm/i915/gt/
A Dintel_rc6.c388 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH | in chv_rc6_enable()
413 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH | in vlv_rc6_enable()
735 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH)); in vlv_residency_raw()
745 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH)); in vlv_residency_raw()
A Dintel_ggtt_fencing.c917 _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB)); in intel_gt_init_swizzling()
921 _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB)); in intel_gt_init_swizzling()
925 _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW)); in intel_gt_init_swizzling()
A Dintel_ring_submission.c127 _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE | in flush_cs_tlb()
171 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); in set_pp_dir()
681 *cs++ = _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE); in load_pd_dir()
730 *cs++ = _MASKED_BIT_ENABLE( in mi_set_context()
1017 _MASKED_BIT_ENABLE(GEN6_PSMI_SLEEP_MSG_DISABLE)); in gen6_bsd_submit_request()
A Dintel_workarounds.c287 wa_add(wal, reg, 0, _MASKED_BIT_ENABLE(val), val, true); in wa_masked_en()
293 wa_mcr_add(wal, reg, 0, _MASKED_BIT_ENABLE(val), val, true); in wa_mcr_masked_en()
640 _MASKED_BIT_ENABLE(FLOAT_BLEND_OPTIMIZATION_ENABLE), in icl_ctx_workarounds_init()
1071 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE), in hsw_gt_workarounds_init()
2480 _MASKED_BIT_ENABLE(ENABLE_EU_COUNT_FOR_TDL_FLUSH), in rcs_engine_wa_init()
2919 0, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH), in rcs_engine_wa_init()
2935 0, _MASKED_BIT_ENABLE(ECO_CONSTANT_BUFFER_SR_DISABLE), in rcs_engine_wa_init()
3124 _MASKED_BIT_ENABLE(ENABLE_PREFETCH_INTO_IC), in general_render_compute_wa_init()
A Dintel_gt.c1118 val = _MASKED_BIT_ENABLE(val); in mmio_invalidate_full()
1130 rb.bit = _MASKED_BIT_ENABLE(rb.bit); in mmio_invalidate_full()
A Dgen6_ppgtt.c70 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); in gen6_ppgtt_enable()
A Dintel_engine_cs.c1494 intel_uncore_write_fw(uncore, mode, _MASKED_BIT_ENABLE(STOP_RING)); in __intel_engine_stop_cs()
1504 _MASKED_BIT_ENABLE(GEN12_GFX_PREFETCH_DISABLE)); in __intel_engine_stop_cs()
2419 _MASKED_BIT_ENABLE(GEN12_RCU_MODE_CCS_ENABLE)); in xehp_enable_ccs_engines()
A Dintel_reset.c586 intel_uncore_write_fw(uncore, reg, _MASKED_BIT_ENABLE(request)); in gen8_engine_reset_prepare()
A Dintel_lrc.c856 ctl = _MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH); in init_common_regs()
A Dintel_execlists_submission.c2931 mode = _MASKED_BIT_ENABLE(GEN11_GFX_DISABLE_LEGACY_MODE); in enable_execlists()
2933 mode = _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE); in enable_execlists()
/linux-6.3-rc2/drivers/gpu/drm/i915/
A Di915_reg_defs.h111 #define _MASKED_BIT_ENABLE(a) ({ typeof(a) _a = (a); _MASKED_FIELD(_a, _a); }) macro
A Dintel_pm.c357 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) : in _intel_set_memory_cxsr()
368 val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) : in _intel_set_memory_cxsr()
4520 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE)); in bdw_init_clock_gating()
4571 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); in ivb_init_clock_gating()
4575 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); in ivb_init_clock_gating()
4577 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); in ivb_init_clock_gating()
4611 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); in vlv_init_clock_gating()
4646 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE)); in chv_init_clock_gating()
4717 _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY)); in gen3_init_clock_gating()
4742 _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE)); in i85x_init_clock_gating()
[all …]
A Di915_perf.c2766 _MASKED_BIT_ENABLE(GEN9_OA_DEBUG_DISABLE_CLK_RATIO_REPORTS | in gen8_enable_metric_set()
2810 _MASKED_BIT_ENABLE(STALL_DOP_GATING_DISABLE)); in gen12_enable_metric_set()
2812 _MASKED_BIT_ENABLE(GEN12_DISABLE_DOP_GATING)); in gen12_enable_metric_set()
2817 _MASKED_BIT_ENABLE(GEN12_OAG_OA_DEBUG_DISABLE_CLK_RATIO_REPORTS | in gen12_enable_metric_set()
4392 val = val & ~_MASKED_BIT_ENABLE(GEN8_ST_PO_DISABLE); in mask_reg_value()
4399 val = val & ~_MASKED_BIT_ENABLE(HSW_WAIT_FOR_RC6_EXIT_ENABLE); in mask_reg_value()
A Dintel_uncore.c125 #define fw_set(d, val) writel(_MASKED_BIT_ENABLE((val)), (d)->reg_set)
A Di915_irq.c2421 …intel_uncore_write(&dev_priv->uncore, SCPD0, _MASKED_BIT_ENABLE(CSTATE_RENDER_CLOCK_GATE_DISABLE)); in i915gm_enable_vblank()
/linux-6.3-rc2/drivers/gpu/drm/i915/pxp/
A Dintel_pxp.c71 _MASKED_BIT_ENABLE(KCR_INIT_ALLOW_DISPLAY_ME_WRITES)); in kcr_pxp_enable()
/linux-6.3-rc2/drivers/gpu/drm/i915/gt/uc/
A Dintel_uc_fw.c930 _MASKED_BIT_ENABLE(dma_flags | START_DMA)); in uc_fw_xfer()
A Dintel_guc_submission.c4072 _MASKED_BIT_ENABLE(GEN11_GFX_DISABLE_LEGACY_MODE)); in start_engine()

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