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Searched refs:_MMIO (Results 1 – 25 of 42) sorted by relevance

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/linux-6.3-rc2/drivers/gpu/drm/i915/gt/
A Dintel_gt_regs.h33 #define RPM_CONFIG0 _MMIO(0xd00)
47 #define RPM_CONFIG1 _MMIO(0xd04)
51 #define RCP_CONFIG _MMIO(0xd08)
98 #define HWS_PGA _MMIO(0x2080)
131 #define NOPID _MMIO(0x2094)
132 #define HWSTAM _MMIO(0x2098)
1427 #define ECR _MMIO(0x11600)
1433 #define EG0 _MMIO(0x11610)
1434 #define EG1 _MMIO(0x11614)
1435 #define EG2 _MMIO(0x11618)
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A Dintel_engine_regs.h11 #define RING_EXCC(base) _MMIO((base) + 0x28)
12 #define RING_TAIL(base) _MMIO((base) + 0x30)
14 #define RING_HEAD(base) _MMIO((base) + 0x34)
18 #define RING_START(base) _MMIO((base) + 0x38)
19 #define RING_CTL(base) _MMIO((base) + 0x3c)
32 #define RING_SYNC_0(base) _MMIO((base) + 0x40)
68 #define IPEIR(base) _MMIO((base) + 0x88)
69 #define IPEHR(base) _MMIO((base) + 0x8c)
70 #define RING_ID(base) _MMIO((base) + 0x8c)
87 #define ACTHD(base) _MMIO((base) + 0xc8)
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/linux-6.3-rc2/drivers/gpu/drm/i915/
A Dintel_gvt_mmio_table.c67 MMIO_D(_MMIO(0x2148)); in iterate_generic_mmio()
90 MMIO_D(_MMIO(0x2124)); in iterate_generic_mmio()
91 MMIO_D(_MMIO(0x20dc)); in iterate_generic_mmio()
93 MMIO_D(_MMIO(0x2088)); in iterate_generic_mmio()
95 MMIO_D(_MMIO(0x2470)); in iterate_generic_mmio()
99 MMIO_D(_MMIO(0x9030)); in iterate_generic_mmio()
100 MMIO_D(_MMIO(0x20a0)); in iterate_generic_mmio()
101 MMIO_D(_MMIO(0x2420)); in iterate_generic_mmio()
102 MMIO_D(_MMIO(0x2430)); in iterate_generic_mmio()
103 MMIO_D(_MMIO(0x2434)); in iterate_generic_mmio()
[all …]
A Dintel_mchbar_regs.h32 #define CSHRDDR3CTL _MMIO(MCHBAR_MIRROR_BASE + 0x1a8)
36 #define DCC _MMIO(MCHBAR_MIRROR_BASE + 0x200)
43 #define DCC2 _MMIO(MCHBAR_MIRROR_BASE + 0x204)
47 #define C0DRB3_BW _MMIO(MCHBAR_MIRROR_BASE + 0x206)
48 #define C1DRB3_BW _MMIO(MCHBAR_MIRROR_BASE + 0x606)
51 #define CLKCFG _MMIO(MCHBAR_MIRROR_BASE + 0xc00)
69 #define HPLLVCO _MMIO(MCHBAR_MIRROR_BASE + 0xc38)
71 #define TSC1 _MMIO(MCHBAR_MIRROR_BASE + 0x1001)
73 #define TR1 _MMIO(MCHBAR_MIRROR_BASE + 0x1006)
74 #define TSFS _MMIO(MCHBAR_MIRROR_BASE + 0x1020)
[all …]
A Di915_perf_oa_regs.h11 #define GEN7_OACONTROL _MMIO(0x2360)
28 #define GEN8_OACTXID _MMIO(0x2364)
30 #define GEN8_OA_DEBUG _MMIO(0x2B04)
36 #define GEN8_OACONTROL _MMIO(0x2B00)
45 #define GEN8_OACTXCONTROL _MMIO(0x2360)
58 #define GEN8_OABUFFER _MMIO(0x2b14)
61 #define GEN7_OASTATUS1 _MMIO(0x2364)
67 #define GEN7_OASTATUS2 _MMIO(0x2368)
71 #define GEN8_OASTATUS _MMIO(0x2b08)
79 #define GEN8_OAHEADPTR _MMIO(0x2B0C)
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A Di915_reg.h964 #define DERRMR _MMIO(0x44050)
988 #define GEN2_IER _MMIO(0x20a0)
989 #define GEN2_IIR _MMIO(0x20a4)
990 #define GEN2_IMR _MMIO(0x20a8)
1005 #define EIR _MMIO(0x20b0)
1006 #define EMR _MMIO(0x20b4)
1007 #define ESR _MMIO(0x20b8)
1026 #define FW_BLC _MMIO(0x20d8)
1407 #define VGA0 _MMIO(0x6000)
1408 #define VGA1 _MMIO(0x6004)
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A Di915_reg_defs.h133 #define _MMIO(r) ((const i915_reg_t){ .reg = (r) }) macro
139 #define INVALID_MMIO_REG _MMIO(0)
A Di915_pvinfo.h117 #define vgtif_reg(x) _MMIO(VGT_PVINFO_PAGE + vgtif_offset(x))
/linux-6.3-rc2/drivers/gpu/drm/i915/gt/uc/
A Dintel_guc_reg.h16 #define GUC_STATUS _MMIO(0xc000)
45 #define DMA_ADDR_0_LOW _MMIO(0xc300)
46 #define DMA_ADDR_0_HIGH _MMIO(0xc304)
47 #define DMA_ADDR_1_LOW _MMIO(0xc308)
48 #define DMA_ADDR_1_HIGH _MMIO(0xc30c)
51 #define DMA_COPY_SIZE _MMIO(0xc310)
52 #define DMA_CTRL _MMIO(0xc314)
70 #define GUC_WOPCM_SIZE _MMIO(0xc050)
80 #define GEN8_GTCR _MMIO(0x4274)
86 #define GUC_ARAT_C6DIS _MMIO(0xA178)
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/linux-6.3-rc2/drivers/gpu/drm/i915/gvt/
A Dreg.h72 (_MMIO(0x50090))) : \
74 (_MMIO(0x50098))) : \
76 (_MMIO(0x5009C))) : \
77 (_MMIO(0x50080))))); })
119 #define PCH_GMBUS0 _MMIO(0xc5100)
120 #define PCH_GMBUS1 _MMIO(0xc5104)
121 #define PCH_GMBUS2 _MMIO(0xc5108)
122 #define PCH_GMBUS3 _MMIO(0xc510c)
123 #define PCH_GMBUS4 _MMIO(0xc5110)
129 #define TRVADR _MMIO(0x4df0)
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A Dhandlers.c713 _MMIO(0xd80),
720 _MMIO(0x2690),
721 _MMIO(0x2694),
722 _MMIO(0x2698),
723 _MMIO(0x2754),
724 _MMIO(0x28a0),
725 _MMIO(0x4de0),
726 _MMIO(0x4de4),
727 _MMIO(0x4dfc),
729 _MMIO(0x7014),
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A Dmmio_context.c110 {RCS0, _MMIO(0xb118), 0, false}, /* GEN8_L3SQCREG4 */
111 {RCS0, _MMIO(0xb11c), 0, false}, /* GEN9_SCRATCH1 */
114 {RCS0, _MMIO(0xe180), 0xffff, true}, /* HALF_SLICE_CHICKEN2 */
115 {RCS0, _MMIO(0xe184), 0xffff, true}, /* GEN8_HALF_SLICE_CHICKEN3 */
116 {RCS0, _MMIO(0xe188), 0xffff, true}, /* GEN9_HALF_SLICE_CHICKEN5 */
117 {RCS0, _MMIO(0xe194), 0xffff, true}, /* GEN9_HALF_SLICE_CHICKEN7 */
118 {RCS0, _MMIO(0xe4f0), 0xffff, true}, /* GEN8_ROW_CHICKEN */
125 {RCS0, _MMIO(0x4dfc), 0, true},
144 {RCS0, _MMIO(0x20D8), 0xffff, true}, /* 0x20d8 */
372 reg = _MMIO(regs[engine->id]); in handle_tlb_pending_event()
/linux-6.3-rc2/drivers/gpu/drm/i915/display/
A Dintel_combo_phy_regs.h27 #define ICL_PORT_CL_DW5(phy) _MMIO(_ICL_PORT_CL_DW(5, phy))
31 #define ICL_PORT_CL_DW10(phy) _MMIO(_ICL_PORT_CL_DW(10, phy))
48 #define ICL_PORT_CL_DW12(phy) _MMIO(_ICL_PORT_CL_DW(12, phy))
56 #define ICL_PORT_COMP_DW0(phy) _MMIO(_ICL_PORT_COMP_DW(0, phy))
59 #define ICL_PORT_COMP_DW1(phy) _MMIO(_ICL_PORT_COMP_DW(1, phy))
61 #define ICL_PORT_COMP_DW3(phy) _MMIO(_ICL_PORT_COMP_DW(3, phy))
73 #define ICL_PORT_COMP_DW8(phy) _MMIO(_ICL_PORT_COMP_DW(8, phy))
76 #define ICL_PORT_COMP_DW9(phy) _MMIO(_ICL_PORT_COMP_DW(9, phy))
78 #define ICL_PORT_COMP_DW10(phy) _MMIO(_ICL_PORT_COMP_DW(10, phy))
111 #define ICL_PORT_TX_DW2_AUX(phy) _MMIO(_ICL_PORT_TX_DW_AUX(2, phy))
[all …]
A Dintel_dmc_regs.h11 #define DMC_PROGRAM(addr, i) _MMIO((addr) + (i) * 4)
21 #define MTL_PIPEDMC_CONTROL _MMIO(0x45250)
67 #define DMC_SSP_BASE _MMIO(0x8F074)
68 #define DMC_HTP_SKL _MMIO(0x8F004)
69 #define DMC_LAST_WRITE _MMIO(0x8F034)
89 #define SKL_DMC_DC3_DC5_COUNT _MMIO(0x80030)
90 #define SKL_DMC_DC5_DC6_COUNT _MMIO(0x8002C)
91 #define BXT_DMC_DC3_DC5_COUNT _MMIO(0x80038)
92 #define TGL_DMC_DEBUG_DC5_COUNT _MMIO(0x101084)
96 #define TGL_DMC_DEBUG3 _MMIO(0x101090)
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A Dintel_display_reg_defs.h25 #define _MMIO_PIPE(pipe, a, b) _MMIO(_PIPE(pipe, a, b))
26 #define _MMIO_PLANE(plane, a, b) _MMIO(_PLANE(plane, a, b))
27 #define _MMIO_TRANS(tran, a, b) _MMIO(_TRANS(tran, a, b))
28 #define _MMIO_PORT(port, a, b) _MMIO(_PORT(port, a, b))
29 #define _MMIO_PLL(pll, a, b) _MMIO(_PLL(pll, a, b))
30 #define _MMIO_PHY(phy, a, b) _MMIO(_PHY(phy, a, b))
34 #define _MMIO_PIPE3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c))
35 #define _MMIO_PORT3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c))
36 #define _MMIO_PHY3(phy, a, b, c) _MMIO(_PHY3(phy, a, b, c))
37 #define _MMIO_PLL3(pll, ...) _MMIO(_PICK(pll, __VA_ARGS__))
[all …]
A Dintel_audio_regs.h11 #define G4X_AUD_CNTL_ST _MMIO(0x620B4)
16 #define G4X_HDMIW_HDMIEDID _MMIO(0x6210C)
29 #define IBX_AUD_CNTL_ST2 _MMIO(0xE20C0)
39 #define CPT_AUD_CNTRL_ST2 _MMIO(0xE50C0)
112 #define HSW_AUD_PIPE_CONV_CFG _MMIO(0x6507c)
124 #define HSW_AUD_CHICKENBIT _MMIO(0x65f10)
127 #define AUD_FREQ_CNTRL _MMIO(0x65900)
128 #define AUD_PIN_BUF_CTL _MMIO(0x48414)
131 #define AUD_TS_CDCLK_M _MMIO(0x65ea0)
133 #define AUD_TS_CDCLK_N _MMIO(0x65ea4)
[all …]
A Dintel_backlight_regs.h24 #define BLC_PWM_CTL2 _MMIO(0x61250) /* 965+ only */
47 #define BLC_PWM_CTL _MMIO(0x61254)
69 #define BLC_HIST_CTL _MMIO(0x61260)
74 #define BLC_PWM_CPU_CTL2 _MMIO(0x48250)
75 #define BLC_PWM_CPU_CTL _MMIO(0x48254)
77 #define HSW_BLC_PWM2_CTL _MMIO(0x48350)
81 #define BLC_PWM_PCH_CTL1 _MMIO(0xc8250)
85 #define BLC_PWM_PCH_CTL2 _MMIO(0xc8254)
106 #define UTIL_PIN_CTL _MMIO(0x48400)
A Dintel_gmbus_regs.h13 #define GPIO(__i915, gpio) _MMIO(GMBUS_MMIO_BASE(__i915) + 0x5010 + 4 * (gpio))
30 #define GMBUS0(__i915) _MMIO(GMBUS_MMIO_BASE(__i915) + 0x5100)
40 #define GMBUS1(__i915) _MMIO(GMBUS_MMIO_BASE(__i915) + 0x5104)
57 #define GMBUS2(__i915) _MMIO(GMBUS_MMIO_BASE(__i915) + 0x5108)
67 #define GMBUS3(__i915) _MMIO(GMBUS_MMIO_BASE(__i915) + 0x510c)
70 #define GMBUS4(__i915) _MMIO(GMBUS_MMIO_BASE(__i915) + 0x5110)
78 #define GMBUS5(__i915) _MMIO(GMBUS_MMIO_BASE(__i915) + 0x5120)
A Dintel_hdcp_regs.h12 #define HDCP_KEY_CONF _MMIO(0x66c00)
16 #define HDCP_KEY_STATUS _MMIO(0x66c04)
22 #define HDCP_AKSV_LO _MMIO(0x66c10)
23 #define HDCP_AKSV_HI _MMIO(0x66c14)
26 #define HDCP_REP_CTL _MMIO(0x66d00)
57 #define HDCP_SHA_V_PRIME_H0 _MMIO(0x66d04)
58 #define HDCP_SHA_V_PRIME_H1 _MMIO(0x66d08)
59 #define HDCP_SHA_V_PRIME_H2 _MMIO(0x66d0C)
60 #define HDCP_SHA_V_PRIME_H3 _MMIO(0x66d10)
61 #define HDCP_SHA_V_PRIME_H4 _MMIO(0x66d14)
[all …]
A Dvlv_dsi_pll_regs.h11 #define MIPIO_TXESC_CLK_DIV1 _MMIO(0x160004)
13 #define MIPIO_TXESC_CLK_DIV2 _MMIO(0x160008)
18 #define BXT_MIPI_CLOCK_CTL _MMIO(0x46090)
81 #define BXT_DSI_PLL_CTL _MMIO(0x161000)
105 #define BXT_DSI_PLL_ENABLE _MMIO(0x46080)
A Dintel_snps_phy_regs.h18 #define _MMIO_SNPS(phy, reg) _MMIO(_SNPS2(phy, reg))
19 #define _MMIO_SNPS_LN(ln, phy, reg) _MMIO(_SNPS2(phy, \
A Dintel_hti_regs.h11 #define HDPORT_STATE _MMIO(0x45050)
A Dintel_dkl_phy_regs.h27 #define DKL_REG_MMIO(__reg) _MMIO((__reg).reg)
199 #define HIP_INDEX_REG(tc_port) _MMIO((tc_port) < 4 ? _HIP_INDEX_REG0 \
A Dvlv_dsi_regs.h17 #define _MMIO_MIPI(port, a, c) _MMIO(_MIPI_PORT(port, a, c))
35 #define BXT_P_DSI_REGULATOR_CFG _MMIO(0x160020)
38 #define BXT_P_DSI_REGULATOR_TX_CTRL _MMIO(0x160054)
475 #define MIPI_READ_DATA_RETURN(port, n) _MMIO(_MIPI(port, _MIPIA_READ_DATA_RETURN0, _MIPIC_READ_DATA…
/linux-6.3-rc2/drivers/gpu/drm/i915/pxp/
A Dintel_pxp_session.c16 #define GEN12_KCR_SIP _MMIO(0x32260) /* KCR hwdrm session in play 0-31 */
19 #define PXP_GLOBAL_TERMINATE _MMIO(0x320f8)

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