/linux-6.3-rc2/arch/arm/mach-pxa/ |
A D | pxa27x-udc.h | 11 #define UDCCR __REG(0x40600000) /* UDC Control Register */ 181 #define UDCDR0 __REG(0x40600300) /* Data Register - EP0 */ 182 #define UDCDRA __REG(0x40600304) /* Data Register - EPA */ 183 #define UDCDRB __REG(0x40600308) /* Data Register - EPB */ 184 #define UDCDRC __REG(0x4060030C) /* Data Register - EPC */ 185 #define UDCDRD __REG(0x40600310) /* Data Register - EPD */ 186 #define UDCDRE __REG(0x40600314) /* Data Register - EPE */ 187 #define UDCDRF __REG(0x40600318) /* Data Register - EPF */ 188 #define UDCDRG __REG(0x4060031C) /* Data Register - EPG */ 189 #define UDCDRH __REG(0x40600320) /* Data Register - EPH */ [all …]
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A D | pxa2xx-regs.h | 41 #define PCMD0 __REG(0x40F00080 + 0 * 4) 42 #define PCMD1 __REG(0x40F00080 + 1 * 4) 43 #define PCMD2 __REG(0x40F00080 + 2 * 4) 44 #define PCMD3 __REG(0x40F00080 + 3 * 4) 45 #define PCMD4 __REG(0x40F00080 + 4 * 4) 46 #define PCMD5 __REG(0x40F00080 + 5 * 4) 47 #define PCMD6 __REG(0x40F00080 + 6 * 4) 48 #define PCMD7 __REG(0x40F00080 + 7 * 4) 49 #define PCMD8 __REG(0x40F00080 + 8 * 4) 50 #define PCMD9 __REG(0x40F00080 + 9 * 4) [all …]
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A D | pxa3xx-regs.h | 26 #define PMCR __REG(0x40F50000) /* Power Manager Control Register */ 27 #define PSR __REG(0x40F50004) /* Power Manager S2 Status Register */ 28 #define PSPR __REG(0x40F50008) /* Power Manager Scratch Pad Register */ 30 #define PWER __REG(0x40F50010) /* Power Manager Wake-up Enable Register */ 31 #define PWSR __REG(0x40F50014) /* Power Manager Wake-up Status Register */ 33 #define DCDCSR __REG(0x40F50080) /* DC-DC Controller Status Register */ 35 #define PCMD(x) __REG(0x40F50110 + ((x) << 2)) 41 #define ARSR __REG(0x40f40004) /* Application Subsystem Reset Status */ 129 #define CKENA __REG(0x4134000C) /* A Clock Enable Register */ 130 #define CKENB __REG(0x41340010) /* B Clock Enable Register */ [all …]
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A D | regs-rtc.h | 11 #define RCNR __REG(0x40900000) /* RTC Count Register */ 12 #define RTAR __REG(0x40900004) /* RTC Alarm Register */ 13 #define RTSR __REG(0x40900008) /* RTC Status Register */ 14 #define RTTR __REG(0x4090000C) /* RTC Timer Trim Register */ 15 #define PIAR __REG(0x40900038) /* Periodic Interrupt Alarm Register */
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A D | pxa-regs.h | 35 # define __REG(x) (*((volatile u32 __iomem *)io_p2v(x))) macro 40 (*(volatile u32 __iomem*)((u32)&__REG(x) + (y))) 46 # define __REG(x) io_p2v(x) macro
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A D | pxa27x.h | 11 #define ARB_CNTRL __REG(0x48000048) /* Arbiter Control Register */
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/linux-6.3-rc2/arch/arm/mach-sa1100/include/mach/ |
A D | SA-1100.h | 884 #define PMCR __REG(0x90020000) /* PM Control Reg. */ 885 #define PSSR __REG(0x90020004) /* PM Sleep Status Reg. */ 886 #define PSPR __REG(0x90020008) /* PM Scratch-Pad Reg. */ 887 #define PWER __REG(0x9002000C) /* PM Wake-up Enable Reg. */ 1025 #define RSRR __REG(0x90030000) /* RC Software Reset Reg. */ 1026 #define RCSR __REG(0x90030004) /* RC Status Reg. */ 1043 #define TUCR __REG(0x90030008) /* Test Unit Control Reg. */ 1369 #define MDCAS0 __REG(0xA0000004) /* DRAM CAS shift reg. 0 */ 1370 #define MDCAS1 __REG(0xA0000008) /* DRAM CAS shift reg. 1 */ 1371 #define MDCAS2 __REG(0xA000000c) /* DRAM CAS shift reg. 2 */ [all …]
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A D | hardware.h | 44 # define __REG(x) (*((volatile unsigned long __iomem *)io_p2v(x))) macro 49 # define __REG(x) io_p2v(x) macro
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/linux-6.3-rc2/drivers/net/ethernet/microchip/sparx5/ |
A D | sparx5_main_regs.h | 58 #define __REG(...) __VA_ARGS__ macro 61 #define ANA_AC_RAM_INIT __REG(TARGET_ANA_AC,\ 77 #define ANA_AC_OWN_UPSID(r) __REG(TARGET_ANA_AC,\ 87 #define ANA_AC_SRC_CFG(g) __REG(TARGET_ANA_AC,\ 91 #define ANA_AC_SRC_CFG1(g) __REG(TARGET_ANA_AC,\ 95 #define ANA_AC_SRC_CFG2(g) __REG(TARGET_ANA_AC,\ 105 #define ANA_AC_PGID_CFG(g) __REG(TARGET_ANA_AC,\ 109 #define ANA_AC_PGID_CFG1(g) __REG(TARGET_ANA_AC,\ 113 #define ANA_AC_PGID_CFG2(g) __REG(TARGET_ANA_AC,\ 123 #define ANA_AC_PGID_MISC_CFG(g) __REG(TARGET_ANA_AC,\ [all …]
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/linux-6.3-rc2/drivers/net/ethernet/microchip/lan966x/ |
A D | lan966x_regs.h | 32 #define __REG(...) __VA_ARGS__ macro 35 #define AFI_PORT_FRM_OUT(g) __REG(TARGET_AFI, 0, 1, 98816, g, 10, 8, 0, 0, 1, 4) 44 #define AFI_PORT_CFG(g) __REG(TARGET_AFI, 0, 1, 98816, g, 10, 8, 4, 0, 1, 4) 59 #define ANA_ADVLEARN __REG(TARGET_ANA, 0, 1, 29824, 0, 1, 244, 0, 0, 1, 4) 68 #define ANA_VLANMASK __REG(TARGET_ANA, 0, 1, 29824, 0, 1, 244, 8, 0, 1, 4) 71 #define ANA_ANAINTR __REG(TARGET_ANA, 0, 1, 29824, 0, 1, 244, 16, 0, 1, 4) 581 #define DEV_CLOCK_CFG(t) __REG(TARGET_DEV, t, 8, 0, 0, 1, 28, 0, 0, 1, 4) 998 #define PTP_WF_HIGH_PERIOD(g) __REG(TARGET_PTP,\ 1006 #define PTP_WF_LOW_PERIOD(g) __REG(TARGET_PTP,\ 1056 #define QS_XTR_GRP_CFG(r) __REG(TARGET_QS, 0, 1, 0, 0, 1, 36, 0, r, 2, 4) [all …]
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/linux-6.3-rc2/drivers/phy/microchip/ |
A D | sparx5_serdes_regs.h | 29 #define __REG(...) __VA_ARGS__ macro 32 #define SD10G_LANE_LANE_01(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 4, 0, 1, 4) 53 #define SD10G_LANE_LANE_02(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 8, 0, 1, 4) 86 #define SD10G_LANE_LANE_03(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 12, 0, 1, 4) 95 #define SD10G_LANE_LANE_04(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 16, 0, 1, 4) 104 #define SD10G_LANE_LANE_06(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 24, 0, 1, 4) 2111 #define SD_CMU_CMU_00(t) __REG(TARGET_SD_CMU, t, 14, 0, 0, 1, 20, 0, 0, 1, 4) 2363 #define SD_LANE_SD_SER_RST(t) __REG(TARGET_SD_LANE, t, 25, 0, 0, 1, 8, 0, 0, 1, 4) 2372 #define SD_LANE_SD_DES_RST(t) __REG(TARGET_SD_LANE, t, 25, 0, 0, 1, 8, 4, 0, 1, 4) 2381 #define SD_LANE_SD_LANE_CFG(t) __REG(TARGET_SD_LANE, t, 25, 8, 0, 1, 8, 0, 0, 1, 4) [all …]
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A D | lan966x_serdes_regs.h | 15 #define __REG(...) __VA_ARGS__ macro 18 #define HSIO_SD_CFG(g) __REG(TARGET_HSIO, 0, 1, 8, g, 3, 32, 0, 0, 1, 4) 111 #define HSIO_MPLL_CFG(g) __REG(TARGET_HSIO, 0, 1, 8, g, 3, 32, 8, 0, 1, 4) 138 #define HSIO_SD_STAT(g) __REG(TARGET_HSIO, 0, 1, 8, g, 3, 32, 12, 0, 1, 4) 165 #define HSIO_HW_CFG __REG(TARGET_HSIO, 0, 1, 104, 0, 1, 52, 0, 0, 1, 4) 210 #define HSIO_RGMII_CFG(r) __REG(TARGET_HSIO, 0, 1, 104, 0, 1, 52, 20, r, 2, 4) 231 #define HSIO_DLL_CFG(r) __REG(TARGET_HSIO, 0, 1, 104, 0, 1, 52, 36, r, 4, 4)
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/linux-6.3-rc2/drivers/net/wireless/mediatek/mt76/mt7915/ |
A D | regs.h | 125 #define __REG(id) (dev->reg.reg_rev[(id)]) macro 138 #define MT_MCU_INT_EVENT __REG(INT_MCU_CMD_EVENT) 570 #define MT_WFDMA0_BASE __REG(WFDMA0_ADDR) 697 #define MT_INT_SOURCE_CSR __REG(INT_SOURCE_CSR) 698 #define MT_INT_MASK_CSR __REG(INT_MASK_CSR) 701 #define MT_INT1_MASK_CSR __REG(INT1_MASK_CSR) 750 #define MT_MCU_CMD __REG(INT_MCU_CMD_SOURCE) 804 #define MT_CBTOP1_PHY_END __REG(CBTOP1_PHY_END) 1007 #define MT_FW_CIRQ_IDX __REG(FW_CIRQ_IDX_ADDR) 1009 #define MT_FW_TASK_ID __REG(FW_TASK_ID_ADDR) [all …]
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/linux-6.3-rc2/arch/xtensa/include/asm/ |
A D | coprocessor.h | 102 __REG ## list (cc, abi, type, name, size, align)
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