| /linux-6.3-rc2/drivers/reset/sti/ |
| A D | reset-stih407.c | 18 #define STIH407_PDN_0(_bit) \ argument
19 _SYSCFG_RST_CH(stih407_core, SYSCFG_5000, _bit, SYSSTAT_5500, _bit)
20 #define STIH407_PDN_1(_bit) \ argument
21 _SYSCFG_RST_CH(stih407_core, SYSCFG_5001, _bit, SYSSTAT_5501, _bit)
22 #define STIH407_PDN_ETH(_bit, _stat) \ argument
57 #define STIH407_SRST_CORE(_reg, _bit) \ argument
58 _SYSCFG_RST_CH_NO_ACK(stih407_core, _reg, _bit)
60 #define STIH407_SRST_SBC(_reg, _bit) \ argument
61 _SYSCFG_RST_CH_NO_ACK(stih407_sbc_reg, _reg, _bit)
63 #define STIH407_SRST_LPM(_reg, _bit) \ argument
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| /linux-6.3-rc2/sound/soc/mediatek/mt8188/ |
| A D | mt8188-audsys-clk.c | 33 .bit = _bit, \
38 #define GATE_AFE(_id, _name, _parent, _reg, _bit) \ argument
39 GATE_AFE_FLAGS(_id, _name, _parent, _reg, _bit, \
42 #define GATE_AUD0(_id, _name, _parent, _bit) \ argument
43 GATE_AFE(_id, _name, _parent, AUDIO_TOP_CON0, _bit)
45 #define GATE_AUD1(_id, _name, _parent, _bit) \ argument
46 GATE_AFE(_id, _name, _parent, AUDIO_TOP_CON1, _bit)
48 #define GATE_AUD3(_id, _name, _parent, _bit) \ argument
51 #define GATE_AUD4(_id, _name, _parent, _bit) \ argument
54 #define GATE_AUD5(_id, _name, _parent, _bit) \ argument
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| /linux-6.3-rc2/sound/soc/mediatek/mt8195/ |
| A D | mt8195-audsys-clk.c | 33 .bit = _bit, \
38 #define GATE_AFE(_id, _name, _parent, _reg, _bit) \ argument
39 GATE_AFE_FLAGS(_id, _name, _parent, _reg, _bit, \
42 #define GATE_AUD0(_id, _name, _parent, _bit) \ argument
43 GATE_AFE(_id, _name, _parent, AUDIO_TOP_CON0, _bit)
45 #define GATE_AUD1(_id, _name, _parent, _bit) \ argument
46 GATE_AFE(_id, _name, _parent, AUDIO_TOP_CON1, _bit)
48 #define GATE_AUD3(_id, _name, _parent, _bit) \ argument
51 #define GATE_AUD4(_id, _name, _parent, _bit) \ argument
54 #define GATE_AUD5(_id, _name, _parent, _bit) \ argument
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| /linux-6.3-rc2/sound/soc/mediatek/mt8186/ |
| A D | mt8186-audsys-clk.c | 27 #define GATE_AFE_FLAGS(_id, _name, _parent, _reg, _bit, _flags, _cgflags) {\ argument
32 .bit = _bit, \
37 #define GATE_AFE(_id, _name, _parent, _reg, _bit) \ argument
38 GATE_AFE_FLAGS(_id, _name, _parent, _reg, _bit, \
41 #define GATE_AUD0(_id, _name, _parent, _bit) \ argument
42 GATE_AFE(_id, _name, _parent, AUDIO_TOP_CON0, _bit)
44 #define GATE_AUD1(_id, _name, _parent, _bit) \ argument
45 GATE_AFE(_id, _name, _parent, AUDIO_TOP_CON1, _bit)
47 #define GATE_AUD2(_id, _name, _parent, _bit) \ argument
48 GATE_AFE(_id, _name, _parent, AUDIO_TOP_CON2, _bit)
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| /linux-6.3-rc2/drivers/clk/meson/ |
| A D | clk-regmap.h | 117 #define __MESON_PCLK(_name, _reg, _bit, _ops, _pname) \ argument
121 .bit_idx = (_bit), \
132 #define MESON_PCLK(_name, _reg, _bit, _pname) \ argument
133 __MESON_PCLK(_name, _reg, _bit, &clk_regmap_gate_ops, _pname)
135 #define MESON_PCLK_RO(_name, _reg, _bit, _pname) \ argument
136 __MESON_PCLK(_name, _reg, _bit, &clk_regmap_gate_ro_ops, _pname)
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| A D | gxbb-aoclk.c | 24 #define GXBB_AO_GATE(_name, _bit) \ argument
28 .bit_idx = (_bit), \
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| A D | axg-aoclk.c | 35 #define AXG_AO_GATE(_name, _bit) \ argument
39 .bit_idx = (_bit), \
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| /linux-6.3-rc2/drivers/clk/renesas/ |
| A D | rzg2l-cpg.h | 189 #define DEF_MOD_BASE(_name, _id, _parent, _off, _bit, _is_coupled) \ argument
195 .bit = (_bit), \
199 #define DEF_MOD(_name, _id, _parent, _off, _bit) \ argument
200 DEF_MOD_BASE(_name, _id, _parent, _off, _bit, false)
202 #define DEF_COUPLED(_name, _id, _parent, _off, _bit) \ argument
203 DEF_MOD_BASE(_name, _id, _parent, _off, _bit, true)
218 #define DEF_RST_MON(_id, _off, _bit, _monbit) \ argument
221 .bit = (_bit), \
224 #define DEF_RST(_id, _off, _bit) \ argument
225 DEF_RST_MON(_id, _off, _bit, -1)
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| /linux-6.3-rc2/arch/xtensa/include/asm/ |
| A D | bitops.h | 102 static inline void arch_##op##_bit(unsigned int bit, volatile unsigned long *p)\
122 arch_test_and_##op##_bit(unsigned int bit, volatile unsigned long *p) \
145 static inline void arch_##op##_bit(unsigned int bit, volatile unsigned long *p)\
166 arch_test_and_##op##_bit(unsigned int bit, volatile unsigned long *p) \
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| /linux-6.3-rc2/drivers/pinctrl/mediatek/ |
| A D | pinctrl-mtk-common.h | 109 #define MTK_PIN_DRV_GRP(_pin, _offset, _bit, _grp) \ argument
113 .bit = _bit, \
157 #define MTK_PIN_IES_SMT_SPEC(_start, _end, _offset, _bit) \ argument
161 .bit = _bit, \
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| /linux-6.3-rc2/Documentation/ |
| A D | atomic_bitops.txt | 20 {set,clear,change}_bit()
25 test_and_{set,clear,change}_bit()
47 The test_and_{}_bit() operations return the original value of the bit.
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| /linux-6.3-rc2/drivers/clk/bcm/ |
| A D | clk-kona.h | 91 #define POLICY(_offset, _bit) \ argument
94 .bit = (_bit), \
375 #define TRIGGER(_offset, _bit) \ argument
378 .bit = (_bit), \
434 #define CCU_LVM_EN(_offset, _bit) \ argument
437 .bit = (_bit), \
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| /linux-6.3-rc2/drivers/reset/ |
| A D | reset-uniphier.c | 28 #define UNIPHIER_RESET(_id, _reg, _bit) \ argument
32 .bit = (_bit), \
35 #define UNIPHIER_RESETX(_id, _reg, _bit) \ argument
39 .bit = (_bit), \
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| /linux-6.3-rc2/arch/sh/kernel/cpu/sh4a/ |
| A D | clock-sh7366.c | 108 #define DIV4(_reg, _bit, _mask, _flags) \ argument
109 SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
128 #define MSTP(_parent, _reg, _bit, _flags) \ argument
129 SH_CLK_MSTP32(_parent, _reg, _bit, _flags)
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| A D | clock-sh7343.c | 105 #define DIV4(_reg, _bit, _mask, _flags) \ argument
106 SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
125 #define MSTP(_parent, _reg, _bit, _flags) \ argument
126 SH_CLK_MSTP32(_parent, _reg, _bit, _flags)
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| A D | clock-sh7757.c | 62 #define DIV4(_bit, _mask, _flags) \ argument
63 SH_CLK_DIV4(&pll_clk, FRQCR, _bit, _mask, _flags)
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| A D | clock-shx3.c | 61 #define DIV4(_bit, _mask, _flags) \ argument
62 SH_CLK_DIV4(&pll_clk, FRQMR1, _bit, _mask, _flags)
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| A D | clock-sh7785.c | 66 #define DIV4(_bit, _mask, _flags) \ argument
67 SH_CLK_DIV4(&pll_clk, FRQMR1, _bit, _mask, _flags)
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| A D | clock-sh7786.c | 67 #define DIV4(_bit, _mask, _flags) \ argument
68 SH_CLK_DIV4(&pll_clk, FRQMR1, _bit, _mask, _flags)
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| /linux-6.3-rc2/drivers/clk/mvebu/ |
| A D | armada-37xx-periph.c | 130 #define PERIPH_GATE(_name, _bit) \ argument
133 .bit_idx = _bit, \
182 #define PERIPH_CLK_FULL_DD(_name, _bit, _shift, _reg1, _reg2, _shift1, _shift2)\ argument
183 static PERIPH_GATE(_name, _bit); \
187 #define PERIPH_CLK_FULL(_name, _bit, _shift, _reg, _shift1, _table) \ argument
188 static PERIPH_GATE(_name, _bit); \
192 #define PERIPH_CLK_GATE_DIV(_name, _bit, _reg, _shift, _table) \ argument
193 static PERIPH_GATE(_name, _bit); \
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| /linux-6.3-rc2/drivers/clk/uniphier/ |
| A D | clk-uniphier.h | 95 #define UNIPHIER_CLK_GATE(_name, _idx, _parent, _reg, _bit) \ argument
103 .bit = (_bit), \
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| /linux-6.3-rc2/arch/sh/kernel/cpu/sh2a/ |
| A D | clock-sh7264.c | 77 #define DIV4(_reg, _bit, _mask, _flags) \ argument
78 SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
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| A D | clock-sh7269.c | 105 #define DIV4(_reg, _bit, _mask, _flags) \ argument
106 SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
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| /linux-6.3-rc2/drivers/staging/rtl8723bs/hal/ |
| A D | odm_interface.h | 38 #define ODM_BIT(_name, _pDM_Odm) _cat(_name, _pDM_Odm->SupportICType, _bit)
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| /linux-6.3-rc2/drivers/clk/ |
| A D | clk-oxnas.c | 89 #define OXNAS_GATE(_name, _bit, _parents) \ argument
91 .bit = (_bit), \
|