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/linux-6.3-rc2/drivers/net/wireless/ath/ath9k/
A Dar9003_hw.c43 if (AR_SREV_9330_11(ah)) { in ar9003_hw_init_mode_regs()
77 if (ah->is_clk_25mhz) in ar9003_hw_init_mode_regs()
117 if (ah->is_clk_25mhz) in ar9003_hw_init_mode_regs()
161 if (!ah->is_clk_25mhz) in ar9003_hw_init_mode_regs()
759 if (AR_SREV_9340(ah)) in ar9003_tx_gain_table_mode4()
794 if (AR_SREV_9340(ah)) in ar9003_tx_gain_table_mode6()
831 modes[idx](ah); in ar9003_tx_gain_table_apply()
910 } else if (AR_SREV_9531_10(ah) || AR_SREV_9531_11(ah)) { in ar9003_rx_gain_table_mode1()
1035 REG_SET_BIT(ah, AR_PCIE_PM_CTRL(ah), AR_PCIE_PM_CTRL_ENA); in ar9003_hw_configpcipowersave()
1036 REG_WRITE(ah, AR_WA(ah), ah->WARegVal); in ar9003_hw_configpcipowersave()
[all …]
A Dhw-ops.h30 ath9k_hw_ops(ah)->config_pci_powersave(ah, power_off); in ath9k_hw_configpcipowersave()
35 ath9k_hw_ops(ah)->rx_enable(ah); in ath9k_hw_rxena()
60 return ath9k_hw_ops(ah)->set_txdesc(ah, ds, i); in ath9k_hw_set_txdesc()
66 return ath9k_hw_ops(ah)->proc_txdesc(ah, ds, ts); in ath9k_hw_txprocdesc()
89 ath9k_hw_ops(ah)->tx99_start(ah, qnum); in ath9k_hw_tx99_start()
94 ath9k_hw_ops(ah)->tx99_stop(ah); in ath9k_hw_tx99_stop()
100 ath9k_hw_ops(ah)->tx99_set_txpower(ah, power); in ath9k_hw_tx99_set_txpower()
125 ath9k_hw_private_ops(ah)->init_hang_checks(ah); in ath9k_hw_init_hang_checks()
185 return ath9k_hw_private_ops(ah)->olc_init(ah); in ath9k_olc_init()
207 return ath9k_hw_private_ops(ah)->rfbus_req(ah); in ath9k_hw_rfbus_req()
[all …]
A Dhw.c269 val = REG_READ(ah, AR_SREV(ah)); in ath9k_hw_read_revisions()
287 srev = REG_READ(ah, AR_SREV(ah)); in ath9k_hw_read_revisions()
609 ah->WARegVal = REG_READ(ah, AR_WA(ah)); in __ath9k_hw_init()
621 REG_WRITE(ah, AR_WA(ah), ah->WARegVal); in __ath9k_hw_init()
636 if (AR_SREV_9271(ah) || AR_SREV_9100(ah) || AR_SREV_9340(ah) || in __ath9k_hw_init()
980 ah->msi_reg = REG_READ(ah, AR_PCIE_MSI(ah)); in ath9k_hw_init_interrupt_masks()
1364 REG_WRITE(ah, AR_WA(ah), ah->WARegVal); in ath9k_hw_set_reset()
1448 REG_WRITE(ah, AR_WA(ah), ah->WARegVal); in ath9k_hw_set_reset_power_on()
1486 REG_WRITE(ah, AR_WA(ah), ah->WARegVal); in ath9k_hw_set_reset_reg()
2184 REG_WRITE(ah, AR_WA(ah), ah->WARegVal); in ath9k_hw_set_power_awake()
[all …]
A Dar9002_hw.c81 if (AR_SREV_9160(ah) || !AR_SREV_5416_22_OR_LATER(ah)) { in ar9002_hw_init_mode_regs()
217 REG_WRITE(ah, INI_RA(&ah->iniPcieSerdes, i, 0), in ar9002_hw_configpcipowersave()
254 val = REG_READ(ah, AR_WA(ah)); in ar9002_hw_configpcipowersave()
266 if (AR_SREV_9285(ah) || AR_SREV_9271(ah) || AR_SREV_9287(ah)) { in ar9002_hw_configpcipowersave()
275 if (AR_SREV_9280(ah) || AR_SREV_9285(ah) || AR_SREV_9287(ah)) { in ar9002_hw_configpcipowersave()
289 REG_WRITE(ah, AR_WA(ah), val); in ar9002_hw_configpcipowersave()
295 if (AR_SREV_9285(ah) || AR_SREV_9271(ah) || AR_SREV_9287(ah)) { in ar9002_hw_configpcipowersave()
311 if (AR_SREV_9285(ah) || AR_SREV_9287(ah)) in ar9002_hw_configpcipowersave()
317 REG_WRITE(ah, AR_WA(ah), val); in ar9002_hw_configpcipowersave()
386 if (AR_SREV_9100(ah) || AR_SREV_9160(ah)) { in ar9002_hw_init_hang_checks()
[all …]
A Dar9002_calib.c138 ah->cal_samples, i, ah->totalPowerMeasI[i], in ar9002_hw_iqcal_collect()
703 ah->cal_list_curr = ah->cal_list; in ar9002_hw_calibrate()
727 ret = ath9k_hw_loadnf(ah, ah->curchan); in ar9002_hw_calibrate()
755 REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL(ah), in ar9285_hw_cl_cal()
860 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL(ah), in ar9002_hw_init_cal()
865 REG_WRITE(ah, AR_PHY_AGC_CONTROL(ah), in ar9002_hw_init_cal()
893 ah->cal_list = ah->cal_list_last = ah->cal_list_curr = NULL; in ar9002_hw_init_cal()
907 INSERT_CAL(ah, &ah->adcgain_caldata); in ar9002_hw_init_cal()
914 INSERT_CAL(ah, &ah->adcdc_caldata); in ar9002_hw_init_cal()
921 INSERT_CAL(ah, &ah->iq_caldata); in ar9002_hw_init_cal()
[all …]
A Dar9003_phy.c252 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah) || in ar9003_hw_spur_mitigate_mrc_cck()
279 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah) || in ar9003_hw_spur_mitigate_mrc_cck()
317 REG_RMW_FIELD(ah, AR_PHY_AGC_CONTROL(ah), in ar9003_hw_spur_mitigate_mrc_cck()
355 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A(ah), in ar9003_hw_spur_ofdm_clear()
726 if (AR_SREV_9340(ah) || AR_SREV_9531(ah) || AR_SREV_9550(ah) || in ar9003_hw_override_ini()
809 if (AR_SREV_9300(ah) || AR_SREV_9580(ah) || AR_SREV_9550(ah)) { in ar9003_doubler_fix()
918 if (AR_SREV_9550(ah) || AR_SREV_9531(ah) || AR_SREV_9561(ah)) { in ar9003_hw_process_ini()
964 ar9003_hw_set_chain_masks(ah, ah->rxchainmask, ah->txchainmask); in ar9003_hw_process_ini()
1478 if (AR_SREV_9300(ah) || AR_SREV_9340(ah) || AR_SREV_9580(ah)) { in ar9003_hw_set_radar_params()
1937 if (AR_SREV_9340(ah) || AR_SREV_9550(ah) || AR_SREV_9531(ah) || in ar9003_hw_attach_phy_ops()
[all …]
A Dar9003_mci.c26 REG_RMW_FIELD(ah, AR_MCI_COMMAND2, in ar9003_mci_reset_req_wakeup()
461 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL(ah), AR_GPIO_JTAG_DISABLE); in ar9003_mci_observation_set_up()
469 REG_WRITE(ah, AR_OBS(ah), 0x4b); in ar9003_mci_observation_set_up()
474 REG_RMW_FIELD(ah, AR_PHY_TEST_CTL_STATUS(ah), in ar9003_mci_observation_set_up()
827 if (AR_SREV_9565(ah)) in ar9003_mci_osla_setup()
848 if (!AR_SREV_9565(ah)) in ar9003_mci_stat_setup()
942 if (AR_SREV_9565(ah)) { in ar9003_mci_reset()
996 ar9003_mci_mute_bt(ah); in ar9003_mci_reset()
1027 ar9003_mci_stat_setup(ah); in ar9003_mci_reset()
1045 ar9003_mci_mute_bt(ah); in ar9003_mci_stop_bt()
[all …]
A Dani.c142 ath9k_hw_update_mibstats(ah, &ah->ah_mibStats); in ath9k_ani_restart()
263 if (!AR_SREV_9300_20_OR_LATER(ah) || AR_SREV_9485(ah) || in ath9k_hw_set_cck_nil()
264 AR_SREV_9565(ah) || AR_SREV_9561(ah)) in ath9k_hw_set_cck_nil()
342 ah->opmode, in ath9k_ani_reset()
357 ah->opmode, in ath9k_ani_reset()
366 ath9k_ani_restart(ah); in ath9k_ani_reset()
387 ath9k_hw_update_mibstats(ah, &ah->ah_mibStats); in ath9k_hw_ani_read_counters()
447 ath9k_hw_update_mibstats(ah, &ah->ah_mibStats); in ath9k_enable_mib_counters()
453 REG_WRITE(ah, AR_MIBC, in ath9k_enable_mib_counters()
470 ath9k_hw_update_mibstats(ah, &ah->ah_mibStats); in ath9k_hw_disable_mib_counters()
[all …]
A Dmac.c26 ah->txok_interrupt_mask, ah->txerr_interrupt_mask, in ath9k_hw_set_txq_interrupts()
27 ah->txdesc_interrupt_mask, ah->txeol_interrupt_mask, in ath9k_hw_set_txq_interrupts()
41 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg); in ath9k_hw_set_txq_interrupts()
792 REG_WRITE(ah, AR_INTR_SYNC_ENABLE(ah), 0); in ath9k_hw_kill_interrupts()
815 if (AR_SREV_9340(ah) || AR_SREV_9550(ah) || AR_SREV_9531(ah) || in __ath9k_hw_enable_interrupts()
844 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE(ah), ah->msi_mask); in __ath9k_hw_enable_interrupts()
845 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK(ah), ah->msi_mask); in __ath9k_hw_enable_interrupts()
852 ah->msi_reg = REG_READ(ah, AR_PCIE_MSI(ah)); in __ath9k_hw_enable_interrupts()
856 AR_PCIE_MSI(ah), ah->msi_reg); in __ath9k_hw_enable_interrupts()
860 REG_WRITE(ah, AR_PCIE_MSI(ah), in __ath9k_hw_enable_interrupts()
[all …]
A Dbtcoex.c82 if (AR_SREV_SOC(ah)) { in ath9k_hw_init_btcoex_hw()
176 REG_CLR_BIT(ah, AR_GPIO_INPUT_EN_VAL(ah), in ath9k_hw_btcoex_init_2wire()
180 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL(ah), in ath9k_hw_btcoex_init_2wire()
185 REG_RMW_FIELD(ah, AR_GPIO_INPUT_MUX1(ah), in ath9k_hw_btcoex_init_2wire()
200 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL(ah), in ath9k_hw_btcoex_init_3wire()
207 REG_RMW_FIELD(ah, AR_GPIO_INPUT_MUX1(ah), in ath9k_hw_btcoex_init_3wire()
210 REG_RMW_FIELD(ah, AR_GPIO_INPUT_MUX1(ah), in ath9k_hw_btcoex_init_3wire()
253 ah->btcoex_hw.mci.config = (AR_SREV_9462(ah)) ? 0x2201 : 0xa4c1; in ath9k_hw_btcoex_init_mci()
290 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) { in ath9k_hw_btcoex_set_weight()
330 if (AR_SREV_SOC(ah)) in ath9k_hw_btcoex_enable_3wire()
[all …]
A Dar9003_wow.c48 REG_READ(ah, AR_CR), REG_READ(ah, AR_DIAG_SW)); in ath9k_hw_set_powermode_wow_sleep()
52 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) { in ath9k_hw_set_powermode_wow_sleep()
64 REG_WRITE(ah, AR_RTC_FORCE_WAKE(ah), AR_RTC_FORCE_WAKE_ON_INT); in ath9k_hw_set_powermode_wow_sleep()
106 if (AR_SREV_9462_20_OR_LATER(ah) || AR_SREV_9565(ah)) { in ath9k_wow_create_keep_alive_pattern()
229 REG_RMW(ah, AR_PCIE_PM_CTRL(ah), AR_PMCTRL_WOW_PME_CLR, in ath9k_hw_wow_wakeup()
255 if (AR_SREV_9462(ah) || AR_SREV_9565(ah) || AR_SREV_9485(ah)) { in ath9k_hw_wow_wakeup()
281 wa_reg = REG_READ(ah, AR_WA(ah)); in ath9k_hw_wow_set_arwr_reg()
286 REG_WRITE(ah, AR_WA(ah), wa_reg); in ath9k_hw_wow_set_arwr_reg()
312 REG_SET_BIT(ah, AR_PCIE_PM_CTRL(ah), AR_PMCTRL_HOST_PME_EN | in ath9k_hw_wow_enable()
417 host_pm_ctrl = REG_READ(ah, AR_PCIE_PM_CTRL(ah)); in ath9k_hw_wow_enable()
[all …]
A Dcalib.c234 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL(ah), in ath9k_hw_start_nfcal()
238 REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL(ah), in ath9k_hw_start_nfcal()
241 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL(ah), in ath9k_hw_start_nfcal()
279 REG_RMW(ah, ah->nf_regs[i], in ath9k_hw_loadnf()
298 REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL(ah), in ath9k_hw_loadnf()
300 REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL(ah), in ath9k_hw_loadnf()
324 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL(ah), in ath9k_hw_loadnf()
327 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL(ah), in ath9k_hw_loadnf()
345 REG_READ(ah, AR_PHY_AGC_CONTROL(ah))); in ath9k_hw_loadnf()
360 REG_RMW(ah, ah->nf_regs[i], in ath9k_hw_loadnf()
[all …]
A Dar5008_phy.c250 if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah)) in ar5008_hw_set_channel()
543 eepMinorRev = ah->eep_ops->get_eeprom_rev(ah); in ar5008_hw_set_rf_regs()
551 ob2GHz = ah->eep_ops->get_eeprom(ah, EEP_OB_2); in ar5008_hw_set_rf_regs()
552 db2GHz = ah->eep_ops->get_eeprom(ah, EEP_DB_2); in ar5008_hw_set_rf_regs()
558 ob5GHz = ah->eep_ops->get_eeprom(ah, EEP_OB_5); in ar5008_hw_set_rf_regs()
559 db5GHz = ah->eep_ops->get_eeprom(ah, EEP_DB_5); in ar5008_hw_set_rf_regs()
681 if (AR_SREV_9100(ah) || AR_SREV_9160(ah)) { in ar5008_hw_override_ini()
746 ah->eep_ops->set_addac(ah, chan); in ar5008_hw_process_ini()
773 if (AR_SREV_9280(ah) || AR_SREV_9287_11_OR_LATER(ah)) in ar5008_hw_process_ini()
898 ath9k_hw_synth_delay(ah, ah->curchan, synthDelay); in ar5008_hw_rfbus_done()
[all …]
A Dar9003_calib.c164 ret = ath9k_hw_loadnf(ah, ah->curchan); in ar9003_hw_calibrate()
349 REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL(ah), in ar9003_hw_dynamic_osdac_selection()
353 REG_WRITE(ah, AR_PHY_AGC_CONTROL(ah), in ar9003_hw_dynamic_osdac_selection()
370 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL(ah), in ar9003_hw_dynamic_osdac_selection()
374 REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL(ah), in ar9003_hw_dynamic_osdac_selection()
390 REG_WRITE(ah, AR_PHY_AGC_CONTROL(ah), in ar9003_hw_dynamic_osdac_selection()
1377 ah->cal_list = ah->cal_list_last = ah->cal_list_curr = NULL; in ar9003_hw_init_cal_common()
1380 INSERT_CAL(ah, &ah->iq_caldata); in ar9003_hw_init_cal_common()
1383 ah->cal_list_curr = ah->cal_list; in ar9003_hw_init_cal_common()
1549 ar9003_hw_set_chain_masks(ah, ah->rxchainmask, ah->txchainmask); in ar9003_hw_init_cal_pcoem()
[all …]
A Dar9002_phy.c112 switch (ah->eep_ops->get_eeprom(ah, EEP_FRAC_N_5G)) { in ar9002_hw_set_channel()
155 ah->curchan = chan; in ar9002_hw_set_channel()
189 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz); in ar9002_hw_spur_mitigate()
227 ENABLE_REGWRITE_BUFFER(ah); in ar9002_hw_spur_mitigate()
277 REGWRITE_BUFFER_FLUSH(ah); in ar9002_hw_spur_mitigate()
297 ah->originalGain[i] = in ar9002_olc_init()
300 ah->PDADCdelta = 0; in ar9002_olc_init()
356 if (AR_SREV_9285(ah)) { in ar9002_hw_set_nf_limits()
491 if (AR_SREV_9280(ah)) in ar9002_hw_spectral_scan_config()
507 if (AR_SREV_9280(ah)) in ar9002_hw_spectral_scan_config()
[all …]
A Dar9003_rtt.c40 REG_WRITE(ah, AR_PHY_RTT_CTRL, 1); in ar9003_hw_rtt_enable()
45 REG_WRITE(ah, AR_PHY_RTT_CTRL, 0); in ar9003_hw_rtt_disable()
50 REG_RMW_FIELD(ah, AR_PHY_RTT_CTRL, in ar9003_hw_rtt_set_mask()
61 REG_RMW_FIELD(ah, AR_PHY_RTT_CTRL, in ar9003_hw_rtt_force_restore()
202 if (ah->caldata) in ar9003_hw_rtt_clear_hist()
210 if (!ah->caldata) in ar9003_hw_rtt_restore()
238 ar9003_hw_rtt_enable(ah); in ar9003_hw_rtt_restore()
245 if (!ath9k_hw_rfbus_req(ah)) { in ar9003_hw_rtt_restore()
251 ar9003_hw_rtt_load_hist(ah); in ar9003_hw_rtt_restore()
255 ath9k_hw_rfbus_done(ah); in ar9003_hw_rtt_restore()
[all …]
/linux-6.3-rc2/drivers/net/wireless/ath/ath5k/
A Dattach.c118 ah->ah_imr = 0; in ath5k_hw_init()
124 ah->ah_current_channel = &ah->channels[0]; in ath5k_hw_init()
129 ath5k_hw_read_srev(ah); in ath5k_hw_init()
130 srev = ah->ah_mac_srev; in ath5k_hw_init()
152 ah->ah_phy_revision = ath5k_hw_reg_read(ah, AR5K_PHY_CHIP_ID) & in ath5k_hw_init()
154 ah->ah_radio_5ghz_revision = ath5k_hw_radio_revision(ah, in ath5k_hw_init()
162 ah->ah_radio_2ghz_revision = ath5k_hw_radio_revision(ah, in ath5k_hw_init()
169 ah->ah_radio_2ghz_revision = ath5k_hw_radio_revision(ah, in ath5k_hw_init()
206 ah->ah_radio_2ghz_revision = ath5k_hw_radio_revision(ah, in ath5k_hw_init()
331 ath5k_hw_set_bssid(ah); in ath5k_hw_init()
[all …]
A Dreset.c156 switch (ah->ah_bwmode) { in ath5k_hw_init_core_clock()
231 switch (ah->ah_bwmode) { in ath5k_hw_init_core_clock()
927 if (ah->ah_bwmode) { in ath5k_hw_tweak_initval_settings()
1023 ath5k_hw_reg_write(ah, in ath5k_hw_commit_eeprom_settings()
1081 ath5k_hw_reg_write(ah, in ath5k_hw_commit_eeprom_settings()
1178 ATH5K_ERR(ah, in ath5k_hw_reset()
1185 ATH5K_ERR(ah, in ath5k_hw_reset()
1191 ATH5K_ERR(ah, in ath5k_hw_reset()
1342 ATH5K_ERR(ah, in ath5k_hw_reset()
1358 ath5k_hw_dma_init(ah); in ath5k_hw_reset()
[all …]
A Dani.c125 ah->ani_state.spur_level = level; in ath5k_ani_set_spur_immunity_level()
147 ah->ani_state.firstep_level = level; in ath5k_ani_set_firstep_level()
186 ah->ani_state.ofdm_weak_sig = on; in ath5k_ani_set_ofdm_weak_signal_detection()
202 ah->ani_state.cck_weak_sig = on; in ath5k_ani_set_cck_weak_signal_detection()
337 ath5k_ani_set_firstep_level(ah, in ath5k_ani_lower_immunity()
344 ath5k_ani_set_firstep_level(ah, in ath5k_ani_lower_immunity()
648 if (ah->ah_version < AR5K_AR5212) in ath5k_ani_init()
657 memset(&ah->ani_state, 0, sizeof(ah->ani_state)); in ath5k_ani_init()
703 ath5k_hw_set_rx_filter(ah, ath5k_hw_get_rx_filter(ah) | in ath5k_ani_init()
709 ath5k_hw_set_rx_filter(ah, ath5k_hw_get_rx_filter(ah) & in ath5k_ani_init()
[all …]
A Dbase.c550 ath5k_hw_set_opmode(ah, ah->opmode); in ath5k_update_bssid_mask_and_opmode()
910 ah->desc = dma_alloc_coherent(ah->dev, ah->desc_len, in ath5k_desc_alloc()
956 dma_free_coherent(ah->dev, ah->desc_len, ah->desc, ah->desc_daddr); in ath5k_desc_alloc()
1005 dma_free_coherent(ah->dev, ah->desc_len, ah->desc, ah->desc_daddr); in ath5k_desc_free()
2054 trace_ath5k_tx(ah, bf->skb, &ah->txqs[ah->bhalq]); in ath5k_beacon_send()
2220 ath5k_hw_set_imr(ah, ah->imask); in ath5k_beacon_config()
2239 ah->nexttbtt += ah->bintval; in ath5k_tasklet_beacon()
2636 common->ah = ah; in ath5k_init_ah()
2726 free_irq(ah->irq, ah); in ath5k_init_ah()
3198 free_irq(ah->irq, ah); in ath5k_deinit_ah()
[all …]
A Dpcu.c122 if (!ah->ah_bwmode) { in ath5k_hw_get_frame_duration()
139 switch (ah->ah_bwmode) { in ath5k_hw_get_frame_duration()
181 switch (ah->ah_bwmode) { in ath5k_hw_get_default_slottime()
212 switch (ah->ah_bwmode) { in ath5k_hw_get_default_sifs()
413 ath5k_hw_reg_write(ah, in ath5k_hw_set_bssid()
416 ath5k_hw_reg_write(ah, in ath5k_hw_set_bssid()
655 switch (ah->opmode) { in ath5k_hw_init_beacon_timers()
957 ath5k_hw_set_bssid(ah); in ath5k_hw_pcu_init()
967 ah->nvifs) in ath5k_hw_pcu_init()
991 ath5k_hw_reg_write(ah, in ath5k_hw_pcu_init()
[all …]
A Dqcu.c492 ah->ah_txq_imr_txok &= ah->ah_txq_status; in ath5k_hw_reset_tx_queue()
493 ah->ah_txq_imr_txerr &= ah->ah_txq_status; in ath5k_hw_reset_tx_queue()
494 ah->ah_txq_imr_txurn &= ah->ah_txq_status; in ath5k_hw_reset_tx_queue()
495 ah->ah_txq_imr_txdesc &= ah->ah_txq_status; in ath5k_hw_reset_tx_queue()
496 ah->ah_txq_imr_txeol &= ah->ah_txq_status; in ath5k_hw_reset_tx_queue()
497 ah->ah_txq_imr_cbrorn &= ah->ah_txq_status; in ath5k_hw_reset_tx_queue()
498 ah->ah_txq_imr_cbrurn &= ah->ah_txq_status; in ath5k_hw_reset_tx_queue()
499 ah->ah_txq_imr_qtrig &= ah->ah_txq_status; in ath5k_hw_reset_tx_queue()
500 ah->ah_txq_imr_nofrm &= ah->ah_txq_status; in ath5k_hw_reset_tx_queue()
502 ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txq_imr_txok, in ath5k_hw_reset_tx_queue()
[all …]
A Ddma.c51 ath5k_hw_reg_read(ah, AR5K_CR); in ath5k_hw_start_rx_dma()
74 ATH5K_DBG(ah, ATH5K_DEBUG_DMA, in ath5k_hw_stop_rx_dma()
101 ATH5K_DBG(ah, ATH5K_DEBUG_DMA, in ath5k_hw_set_rxdp()
260 ath5k_hw_reg_write(ah, in ath5k_hw_stop_tx_dma()
266 ath5k_hw_reg_write(ah, in ath5k_hw_stop_tx_dma()
461 imr = ath5k_hw_set_imr(ah, ah->ah_imr & ~AR5K_INT_GLOBAL); in ath5k_hw_update_tx_triglevel()
488 ath5k_hw_set_imr(ah, imr); in ath5k_hw_update_tx_triglevel()
744 old_mask = ah->ah_imr; in ath5k_hw_set_imr()
814 ah->ah_imr = new_mask; in ath5k_hw_set_imr()
865 ath5k_hw_set_imr(ah, ah->ah_imr); in ath5k_hw_dma_init()
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A Drfkill.c42 ah->rf_kill.gpio, ah->rf_kill.polarity); in ath5k_rfkill_disable()
43 ath5k_hw_set_gpio_output(ah, ah->rf_kill.gpio); in ath5k_rfkill_disable()
44 ath5k_hw_set_gpio(ah, ah->rf_kill.gpio, !ah->rf_kill.polarity); in ath5k_rfkill_disable()
51 ah->rf_kill.gpio, ah->rf_kill.polarity); in ath5k_rfkill_enable()
52 ath5k_hw_set_gpio_output(ah, ah->rf_kill.gpio); in ath5k_rfkill_enable()
53 ath5k_hw_set_gpio(ah, ah->rf_kill.gpio, ah->rf_kill.polarity); in ath5k_rfkill_enable()
60 ath5k_hw_set_gpio_input(ah, ah->rf_kill.gpio); in ath5k_rfkill_set_intr()
61 curval = ath5k_hw_get_gpio(ah, ah->rf_kill.gpio); in ath5k_rfkill_set_intr()
62 ath5k_hw_set_gpio_intr(ah, ah->rf_kill.gpio, enable ? in ath5k_rfkill_set_intr()
71 return ath5k_hw_get_gpio(ah, ah->rf_kill.gpio) == in ath5k_is_rfkill_set()
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A Dphy.c622 if (ah->ah_gain.g_current >= ah->ah_gain.g_high) { in ath5k_hw_rf_gainf_adjust()
628 for (ah->ah_gain.g_target = ah->ah_gain.g_current; in ath5k_hw_rf_gainf_adjust()
629 ah->ah_gain.g_target >= ah->ah_gain.g_high && in ath5k_hw_rf_gainf_adjust()
640 if (ah->ah_gain.g_current <= ah->ah_gain.g_low) { in ath5k_hw_rf_gainf_adjust()
646 for (ah->ah_gain.g_target = ah->ah_gain.g_current; in ath5k_hw_rf_gainf_adjust()
647 ah->ah_gain.g_target <= ah->ah_gain.g_low && in ath5k_hw_rf_gainf_adjust()
661 ret, ah->ah_gain.g_step_idx, ah->ah_gain.g_current, in ath5k_hw_rf_gainf_adjust()
717 ah->ah_gain.g_current >= ah->ah_gain.g_f_corr ? in ath5k_hw_gainf_calibrate()
718 (ah->ah_gain.g_current - ah->ah_gain.g_f_corr) : in ath5k_hw_gainf_calibrate()
888 ah->ah_rf_banks = kmalloc_array(ah->ah_rf_banks_size, in ath5k_hw_rfregs_init()
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