| /linux-6.3-rc2/drivers/gpu/drm/amd/amdgpu/ |
| A D | amdgpu_virt.h | 271 #define amdgpu_sriov_vf(adev) \ macro
281 (amdgpu_sriov_vf((adev)) && !amdgpu_sriov_runtime((adev)))
284 (amdgpu_sriov_vf((adev)) && \
288 (amdgpu_sriov_vf((adev)) && \
292 (amdgpu_sriov_vf((adev)) && \
296 (amdgpu_sriov_vf((adev)) && \
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| A D | psp_v11_0_8.c | 37 if (amdgpu_sriov_vf(adev)) { in psp_v11_0_8_ring_stop()
68 if (amdgpu_sriov_vf(adev)) { in psp_v11_0_8_ring_create()
150 if (amdgpu_sriov_vf(adev)) in psp_v11_0_8_ring_get_wptr()
162 if (amdgpu_sriov_vf(adev)) { in psp_v11_0_8_ring_set_wptr()
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| A D | psp_v12_0.c | 191 if (amdgpu_sriov_vf(psp->adev)) { in psp_v12_0_ring_create()
243 if (amdgpu_sriov_vf(adev)) in psp_v12_0_ring_stop()
254 if (amdgpu_sriov_vf(adev)) in psp_v12_0_ring_stop()
321 if (amdgpu_sriov_vf(adev)) in psp_v12_0_ring_get_wptr()
333 if (amdgpu_sriov_vf(adev)) { in psp_v12_0_ring_set_wptr()
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| A D | psp_v3_1.c | 196 if (amdgpu_sriov_vf(adev)) { in psp_v3_1_ring_create()
258 if (amdgpu_sriov_vf(adev)) in psp_v3_1_ring_stop()
269 if (amdgpu_sriov_vf(adev)) in psp_v3_1_ring_stop()
345 if (amdgpu_sriov_vf(adev)) in psp_v3_1_ring_get_wptr()
356 if (amdgpu_sriov_vf(adev)) { in psp_v3_1_ring_set_wptr()
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| A D | athub_v1_0.c | 68 if (amdgpu_sriov_vf(adev)) in athub_v1_0_set_clockgating()
94 if (amdgpu_sriov_vf(adev)) in athub_v1_0_get_clockgating()
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| A D | psp_v13_0_4.c | 200 if (amdgpu_sriov_vf(adev)) { in psp_v13_0_4_ring_stop()
231 if (amdgpu_sriov_vf(adev)) { in psp_v13_0_4_ring_create()
313 if (amdgpu_sriov_vf(adev)) in psp_v13_0_4_ring_get_wptr()
325 if (amdgpu_sriov_vf(adev)) { in psp_v13_0_4_ring_set_wptr()
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| A D | mmhub_v1_0.c | 113 if (amdgpu_sriov_vf(adev)) in mmhub_v1_0_init_system_aperture_regs()
159 if (amdgpu_sriov_vf(adev)) in mmhub_v1_0_init_cache_regs()
211 if (amdgpu_sriov_vf(adev)) in mmhub_v1_0_disable_identity_aperture()
302 if (amdgpu_sriov_vf(adev)) in mmhub_v1_0_update_power_gating()
313 if (amdgpu_sriov_vf(adev)) { in mmhub_v1_0_gart_enable()
359 if (!amdgpu_sriov_vf(adev)) { in mmhub_v1_0_gart_disable()
378 if (amdgpu_sriov_vf(adev)) in mmhub_v1_0_set_fault_enable_default()
529 if (amdgpu_sriov_vf(adev)) in mmhub_v1_0_set_clockgating()
554 if (amdgpu_sriov_vf(adev)) in mmhub_v1_0_get_clockgating()
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| A D | amdgpu_psp.c | 101 if (amdgpu_sriov_vf(adev)) { in psp_check_pmfw_centralized_cstate_management()
228 if (amdgpu_sriov_vf(adev)) in psp_early_init()
703 if (amdgpu_sriov_vf(psp->adev)) in psp_prep_tmr_cmd_buf()
831 if (amdgpu_sriov_vf(psp->adev)) in psp_prep_tmr_unload_cmd_buf()
867 if (amdgpu_sriov_vf(psp->adev)) in psp_get_fw_attestation_records_addr()
893 if (amdgpu_sriov_vf(adev)) in psp_boot_config_get()
918 if (amdgpu_sriov_vf(adev)) in psp_boot_config_set()
1536 if (amdgpu_sriov_vf(adev)) in psp_ras_initialize()
1987 if (!amdgpu_sriov_vf(adev)) { in psp_hw_start()
3343 if (!amdgpu_sriov_vf(adev)) { in psp_init_cap_microcode()
[all …]
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| A D | gmc_v11_0.c | 105 if (!amdgpu_sriov_vf(adev)) { in gmc_v11_0_process_interrupt()
133 if (!amdgpu_sriov_vf(adev)) in gmc_v11_0_process_interrupt()
155 if (!amdgpu_sriov_vf(adev)) { in gmc_v11_0_set_irq_funcs()
172 (!amdgpu_sriov_vf(adev))); in gmc_v11_0_use_invalidate_semaphore()
254 !amdgpu_sriov_vf(adev)) { in gmc_v11_0_flush_vm_hub()
293 (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev))) { in gmc_v11_0_flush_gpu_tlb()
679 if (amdgpu_sriov_vf(adev)) in gmc_v11_0_vram_gtt_location()
802 if (!amdgpu_sriov_vf(adev)) { in gmc_v11_0_sw_init()
951 if (amdgpu_sriov_vf(adev)) { in gmc_v11_0_hw_fini()
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| A D | amdgpu_device.c | 1214 if (amdgpu_sriov_vf(adev)) in amdgpu_device_resize_fb_bar()
1289 if (amdgpu_sriov_vf(adev)) in amdgpu_device_need_post()
2426 if (amdgpu_sriov_vf(adev)) in amdgpu_device_ip_init()
2510 if (amdgpu_sriov_vf(adev)) in amdgpu_device_ip_init()
3102 if (amdgpu_sriov_vf(adev)) in amdgpu_device_ip_suspend()
3450 if (amdgpu_sriov_vf(adev)) in amdgpu_device_get_job_timeout_settings()
3721 if (amdgpu_sriov_vf(adev)) in amdgpu_device_init()
3911 if (amdgpu_sriov_vf(adev)) in amdgpu_device_init()
4170 if (amdgpu_sriov_vf(adev)) in amdgpu_device_suspend()
4297 if (amdgpu_sriov_vf(adev)) in amdgpu_device_ip_check_soft_reset()
[all …]
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| A D | amdgpu_vf_error.c | 36 if (!amdgpu_sriov_vf(adev)) in amdgpu_vf_error_put()
57 if ((NULL == adev) || (!amdgpu_sriov_vf(adev)) || in amdgpu_vf_error_trans_all()
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| A D | nv.c | 225 if (amdgpu_sriov_vf(adev)) { in nv_query_video_codecs()
735 if (!amdgpu_sriov_vf(adev)) { in nv_common_early_init()
831 if (amdgpu_sriov_vf(adev)) in nv_common_early_init()
852 if (amdgpu_sriov_vf(adev)) { in nv_common_early_init()
1034 if (amdgpu_sriov_vf(adev)) { in nv_common_early_init()
1046 if (amdgpu_sriov_vf(adev)) { in nv_common_late_init()
1070 if (amdgpu_sriov_vf(adev)) in nv_common_sw_init()
1101 if (adev->nbio.funcs->remap_hdp_registers && !amdgpu_sriov_vf(adev)) in nv_common_hw_init()
1153 if (amdgpu_sriov_vf(adev)) in nv_common_set_clockgating_state()
1190 if (amdgpu_sriov_vf(adev)) in nv_common_get_clockgating_state()
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| A D | sdma_v5_0.c | 205 if (amdgpu_sriov_vf(adev)) in sdma_v5_0_init_golden_registers()
626 if (!amdgpu_sriov_vf(adev)) { in sdma_v5_0_ctx_switch_enable()
640 if (!amdgpu_sriov_vf(adev)) in sdma_v5_0_ctx_switch_enable()
664 if (amdgpu_sriov_vf(adev)) in sdma_v5_0_enable()
697 if (!amdgpu_sriov_vf(adev)) in sdma_v5_0_gfx_resume()
774 if (amdgpu_sriov_vf(adev)) in sdma_v5_0_gfx_resume()
909 if (amdgpu_sriov_vf(adev)) { in sdma_v5_0_start()
1433 if (amdgpu_sriov_vf(adev)) { in sdma_v5_0_hw_fini()
1552 if (!amdgpu_sriov_vf(adev)) { in sdma_v5_0_set_trap_irq_state()
1700 if (amdgpu_sriov_vf(adev)) in sdma_v5_0_set_clockgating_state()
[all …]
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| A D | mmhub_v2_0.c | 223 if (!amdgpu_sriov_vf(adev)) { in mmhub_v2_0_init_system_aperture_regs()
281 if (amdgpu_sriov_vf(adev)) in mmhub_v2_0_init_cache_regs()
342 if (amdgpu_sriov_vf(adev)) in mmhub_v2_0_disable_identity_aperture()
480 if (amdgpu_sriov_vf(adev)) in mmhub_v2_0_set_fault_enable_default()
651 if (amdgpu_sriov_vf(adev)) in mmhub_v2_0_set_clockgating()
676 if (amdgpu_sriov_vf(adev)) in mmhub_v2_0_get_clockgating()
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| A D | mmhub_v3_0.c | 172 if (amdgpu_sriov_vf(adev)) in mmhub_v3_0_init_system_aperture_regs()
238 if (amdgpu_sriov_vf(adev)) in mmhub_v3_0_init_cache_regs()
299 if (amdgpu_sriov_vf(adev)) in mmhub_v3_0_disable_identity_aperture()
437 if (amdgpu_sriov_vf(adev)) in mmhub_v3_0_set_fault_enable_default()
620 if (amdgpu_sriov_vf(adev)) in mmhub_v3_0_set_clockgating()
638 if (amdgpu_sriov_vf(adev)) in mmhub_v3_0_get_clockgating()
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| A D | psp_v11_0.c | 267 if (amdgpu_sriov_vf(adev)) in psp_v11_0_ring_stop()
278 if (amdgpu_sriov_vf(adev)) in psp_v11_0_ring_stop()
296 if (amdgpu_sriov_vf(adev)) { in psp_v11_0_ring_create()
569 if (amdgpu_sriov_vf(adev)) in psp_v11_0_ring_get_wptr()
581 if (amdgpu_sriov_vf(adev)) { in psp_v11_0_ring_set_wptr()
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| A D | mmhub_v3_0_2.c | 170 if (!amdgpu_sriov_vf(adev)) { in mmhub_v3_0_2_init_system_aperture_regs()
230 if (amdgpu_sriov_vf(adev)) in mmhub_v3_0_2_init_cache_regs()
291 if (amdgpu_sriov_vf(adev)) in mmhub_v3_0_2_disable_identity_aperture()
429 if (amdgpu_sriov_vf(adev)) in mmhub_v3_0_2_set_fault_enable_default()
546 if (amdgpu_sriov_vf(adev)) in mmhub_v3_0_2_set_clockgating()
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| A D | gmc_v9_0.c | 612 if (amdgpu_sriov_vf(adev)) in gmc_v9_0_process_interrupt()
702 if (!amdgpu_sriov_vf(adev) && in gmc_v9_0_set_irq_funcs()
743 (!amdgpu_sriov_vf(adev)) && in gmc_v9_0_use_invalidate_semaphore()
807 (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev)) && in gmc_v9_0_flush_gpu_tlb()
1459 if (!amdgpu_sriov_vf(adev) && in gmc_v9_0_late_init()
1654 if (amdgpu_sriov_vf(adev)) in gmc_v9_0_sw_init()
1708 if (amdgpu_sriov_vf(adev)) in gmc_v9_0_sw_init()
1745 if (!amdgpu_sriov_vf(adev) && in gmc_v9_0_sw_init()
1823 if (amdgpu_sriov_vf(adev)) in gmc_v9_0_init_golden_registers()
1932 if (!amdgpu_sriov_vf(adev)) { in gmc_v9_0_hw_init()
[all …]
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| A D | gmc_v10_0.c | 146 if (!amdgpu_sriov_vf(adev)) { in gmc_v10_0_process_interrupt()
177 if (!amdgpu_sriov_vf(adev)) in gmc_v10_0_process_interrupt()
199 if (!amdgpu_sriov_vf(adev)) { in gmc_v10_0_set_irq_funcs()
217 (!amdgpu_sriov_vf(adev))); in gmc_v10_0_use_invalidate_semaphore()
347 (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev)) && in gmc_v10_0_flush_gpu_tlb()
430 u32 usec_timeout = amdgpu_sriov_vf(adev) ? SRIOV_USEC_TIMEOUT : adev->usec_timeout; in gmc_v10_0_flush_gpu_tlb_pasid()
980 if (!amdgpu_sriov_vf(adev)) { in gmc_v10_0_sw_init()
1158 if (amdgpu_sriov_vf(adev)) { in gmc_v10_0_hw_fini()
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| A D | psp_v13_0.c | 84 if (!amdgpu_sriov_vf(adev)) { in psp_v13_0_init_microcode()
267 if (amdgpu_sriov_vf(adev)) { in psp_v13_0_ring_stop()
298 if (amdgpu_sriov_vf(adev)) { in psp_v13_0_ring_create()
380 if (amdgpu_sriov_vf(adev)) in psp_v13_0_ring_get_wptr()
392 if (amdgpu_sriov_vf(adev)) { in psp_v13_0_ring_set_wptr()
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| A D | amdgpu_sdma.c | 75 if (amdgpu_sriov_vf(adev) || vmid == 0 || !amdgpu_mcbp) in amdgpu_sdma_get_csa_mc_addr()
129 if (amdgpu_sriov_vf(adev)) in amdgpu_sdma_process_ras_data_cb()
242 if (amdgpu_sriov_vf(adev)) in amdgpu_sdma_init_microcode()
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| A D | gfxhub_v1_0.c | 100 if (!amdgpu_sriov_vf(adev) || adev->asic_type <= CHIP_VEGA10) { in gfxhub_v1_0_init_system_aperture_regs()
327 if (!amdgpu_sriov_vf(adev)) in gfxhub_v1_0_gart_enable()
331 if (!amdgpu_sriov_vf(adev)) in gfxhub_v1_0_gart_enable()
350 if (amdgpu_sriov_vf(adev)) in gfxhub_v1_0_gart_disable()
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| A D | navi10_ih.c | 123 if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) { in force_update_wptr_for_self_int()
133 if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) { in force_update_wptr_for_self_int()
168 if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) { in navi10_ih_toggle_ring_interrupts()
282 if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) { in navi10_ih_enable_ring()
496 if (amdgpu_sriov_vf(adev)) in navi10_ih_set_rptr()
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| A D | soc15.c | 933 if (!amdgpu_sriov_vf(adev)) { in soc15_common_early_init()
1173 if (amdgpu_sriov_vf(adev)) { in soc15_common_early_init()
1185 if (amdgpu_sriov_vf(adev)) in soc15_common_late_init()
1195 if (amdgpu_sriov_vf(adev)) in soc15_common_sw_init()
1220 if (!amdgpu_sriov_vf(adev)) { in soc15_sdma_doorbell_range_init()
1243 if (adev->nbio.funcs->remap_hdp_registers && !amdgpu_sriov_vf(adev)) in soc15_common_hw_init()
1265 if (amdgpu_sriov_vf(adev)) in soc15_common_hw_fini()
1359 if (amdgpu_sriov_vf(adev)) in soc15_common_set_clockgating_state()
1411 if (amdgpu_sriov_vf(adev)) in soc15_common_get_clockgating_state()
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| A D | sdma_v5_2.c | 438 if (!amdgpu_sriov_vf(adev)) { in sdma_v5_2_ctx_switch_enable()
466 if (!amdgpu_sriov_vf(adev)) { in sdma_v5_2_enable()
498 if (!amdgpu_sriov_vf(adev)) in sdma_v5_2_gfx_resume()
548 if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */ in sdma_v5_2_gfx_resume()
570 if (amdgpu_sriov_vf(adev)) in sdma_v5_2_gfx_resume()
578 if (!amdgpu_sriov_vf(adev)) { in sdma_v5_2_gfx_resume()
740 if (amdgpu_sriov_vf(adev)) { in sdma_v5_2_start()
1291 if (amdgpu_sriov_vf(adev)) { in sdma_v5_2_hw_fini()
1404 if (!amdgpu_sriov_vf(adev)) { in sdma_v5_2_set_trap_irq_state()
1584 if (amdgpu_sriov_vf(adev)) in sdma_v5_2_set_clockgating_state()
[all …]
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