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Searched refs:aud_2_parents (Results 1 – 9 of 9) sorted by relevance

/linux-6.3-rc2/drivers/clk/mediatek/
A Dclk-mt6795-topckgen.c39 static const char * const aud_2_parents[] = { variable
496 TOP_MUX_GATE(CLK_TOP_AUD_2_SEL, "aud_2_sel", aud_2_parents, 0xb0, 0, 2, 7, 0),
A Dclk-mt8173-topckgen.c314 static const char * const aud_2_parents[] = { variable
585 MUX_GATE(CLK_TOP_AUD_2_SEL, "aud_2_sel", aud_2_parents, 0x00b0, 0, 2, 7),
A Dclk-mt8186-topckgen.c176 static const char * const aud_2_parents[] = { variable
548 aud_2_parents, 0x0080, 0x0084, 0x0088, 16, 1, 23, 0x0004, 18),
A Dclk-mt6797.c278 static const char * const aud_2_parents[] = { variable
368 MUX_GATE(CLK_TOP_MUX_AUD_2, "aud_2_sel", aud_2_parents,
A Dclk-mt6779.c548 static const char * const aud_2_parents[] = { variable
760 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_2, "aud_2_sel", aud_2_parents,
A Dclk-mt2712.c483 static const char * const aud_2_parents[] = { variable
801 aud_2_parents, 0x0b0, 0, 2, 7),
A Dclk-mt8183.c439 static const char * const aud_2_parents[] = { variable
582 aud_2_parents, 0xe0,
A Dclk-mt8192.c431 static const char * const aud_2_parents[] = { variable
663 aud_2_parents, 0x0e0, 0x0e4, 0x0e8, 8, 1, 15, 0x008, 22),
A Dclk-mt8365.c222 static const char * const aud_2_parents[] = { variable
466 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_2_SEL, "aud_2_sel", aud_2_parents,

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