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/linux-6.3-rc2/drivers/net/wireless/quantenna/qtnfmac/pcie/
A Dpearl_pcie_regs.h8 #define PCIE_HDP_CTRL(base) ((base) + 0x2c00) argument
9 #define PCIE_HDP_AXI_CTRL(base) ((base) + 0x2c04) argument
10 #define PCIE_HDP_HOST_WR_DESC0(base) ((base) + 0x2c10) argument
21 #define PCIE_HDP_INT_EN(base) ((base) + 0x2c3c) argument
35 #define PCIE_HDP_CFG0(base) ((base) + 0x2c80) argument
36 #define PCIE_HDP_CFG1(base) ((base) + 0x2c84) argument
37 #define PCIE_HDP_CFG2(base) ((base) + 0x2c88) argument
38 #define PCIE_HDP_CFG3(base) ((base) + 0x2c8c) argument
39 #define PCIE_HDP_CFG4(base) ((base) + 0x2c90) argument
47 #define PCIE_INT(base) ((base) + 0x2cb0) argument
[all …]
A Dtopaz_pcie_regs.h8 #define PCIE_DMA_WR_INTR_STATUS(base) ((base) + 0x9bc) argument
9 #define PCIE_DMA_WR_INTR_MASK(base) ((base) + 0x9c4) argument
10 #define PCIE_DMA_WR_INTR_CLR(base) ((base) + 0x9c8) argument
11 #define PCIE_DMA_WR_ERR_STATUS(base) ((base) + 0x9cc) argument
15 #define PCIE_DMA_RD_INTR_STATUS(base) ((base) + 0x310) argument
16 #define PCIE_DMA_RD_INTR_MASK(base) ((base) + 0x319) argument
17 #define PCIE_DMA_RD_INTR_CLR(base) ((base) + 0x31c) argument
24 #define TOPAZ_LH_IPC4_INT(base) ((base) + 0x13C) argument
25 #define TOPAZ_LH_IPC4_INT_MASK(base) ((base) + 0x140) argument
34 #define TOPAZ_CTL_M2L_INT(base) ((base) + 0x2C) argument
[all …]
/linux-6.3-rc2/drivers/gpu/drm/i915/gt/
A Dintel_engine_regs.h11 #define RING_EXCC(base) _MMIO((base) + 0x28) argument
12 #define RING_TAIL(base) _MMIO((base) + 0x30) argument
14 #define RING_HEAD(base) _MMIO((base) + 0x34) argument
18 #define RING_START(base) _MMIO((base) + 0x38) argument
19 #define RING_CTL(base) _MMIO((base) + 0x3c) argument
32 #define RING_SYNC_0(base) _MMIO((base) + 0x40) argument
33 #define RING_SYNC_1(base) _MMIO((base) + 0x44) argument
34 #define RING_SYNC_2(base) _MMIO((base) + 0x48) argument
68 #define IPEIR(base) _MMIO((base) + 0x88) argument
69 #define IPEHR(base) _MMIO((base) + 0x8c) argument
[all …]
/linux-6.3-rc2/drivers/clk/imx/
A Dclk-imx7d.c383 void __iomem *base; in imx7d_clocks_init() local
398 base = of_iomap(np, 0); in imx7d_clocks_init()
399 WARN_ON(!base); in imx7d_clocks_init()
489 base = of_iomap(np, 0); in imx7d_clocks_init()
490 WARN_ON(!base); in imx7d_clocks_init()
572 hws[IMX7D_DRAM_ROOT_CG] = imx_clk_hw_gate3("dram_cg", "dram_src", base + 0x9880, 28); in imx7d_clocks_init()
583 hws[IMX7D_SAI1_ROOT_CG] = imx_clk_hw_gate3("sai1_cg", "sai1_src", base + 0xa500, 28); in imx7d_clocks_init()
584 hws[IMX7D_SAI2_ROOT_CG] = imx_clk_hw_gate3("sai2_cg", "sai2_src", base + 0xa580, 28); in imx7d_clocks_init()
585 hws[IMX7D_SAI3_ROOT_CG] = imx_clk_hw_gate3("sai3_cg", "sai3_src", base + 0xa600, 28); in imx7d_clocks_init()
592 hws[IMX7D_EIM_ROOT_CG] = imx_clk_hw_gate3("eim_cg", "eim_src", base + 0xa980, 28); in imx7d_clocks_init()
[all …]
A Dclk-imx6sll.c82 void __iomem *base; in imx6sll_clocks_init() local
102 base = of_iomap(np, 0); in imx6sll_clocks_init()
104 WARN_ON(!base); in imx6sll_clocks_init()
191 base = of_iomap(np, 0); in imx6sll_clocks_init()
192 WARN_ON(!base); in imx6sll_clocks_init()
218 …hws[IMX6SLL_CLK_PERIPH] = imx_clk_hw_busy_mux("periph", base + 0x14, 25, 1, base + 0x48, 5, peri… in imx6sll_clocks_init()
244 …hws[IMX6SLL_CLK_ARM] = imx_clk_hw_busy_divider("arm", "pll1_sw", base + 0x10, 0, 3, base + 0x48… in imx6sll_clocks_init()
245 …K_MMDC_PODF] = imx_clk_hw_busy_divider("mmdc_podf", "periph2", base + 0x14, 3, 3, base + 0x48, … in imx6sll_clocks_init()
246 …hws[IMX6SLL_CLK_AXI_PODF] = imx_clk_hw_busy_divider("axi", "axi_sel", base + 0x14, 16, 3, base +… in imx6sll_clocks_init()
247 …hws[IMX6SLL_CLK_AHB] = imx_clk_hw_busy_divider("ahb", "periph", base + 0x14, 10, 3, base + 0x48… in imx6sll_clocks_init()
[all …]
A Dclk-imx8ulp.c53 void __iomem *base; member
134 pcc_reset->base = base; in imx8ulp_pcc_reset_init()
150 void __iomem *base; in imx8ulp_clk_cgc1_init() local
165 return PTR_ERR(base); in imx8ulp_clk_cgc1_init()
234 void __iomem *base; in imx8ulp_clk_cgc2_init() local
247 return PTR_ERR(base); in imx8ulp_clk_cgc2_init()
316 void __iomem *base; in imx8ulp_clk_pcc3_init() local
330 return PTR_ERR(base); in imx8ulp_clk_pcc3_init()
399 void __iomem *base; in imx8ulp_clk_pcc4_init() local
413 return PTR_ERR(base); in imx8ulp_clk_pcc4_init()
[all …]
A Dclk-imx6sl.c185 void __iomem *base; in imx6sl_clocks_init() local
203 base = of_iomap(np, 0); in imx6sl_clocks_init()
204 WARN_ON(!base); in imx6sl_clocks_init()
206 anatop_base = base; in imx6sl_clocks_init()
289 base = of_iomap(np, 0); in imx6sl_clocks_init()
290 WARN_ON(!base); in imx6sl_clocks_init()
291 ccm_base = base; in imx6sl_clocks_init()
364 …K_AHB] = imx_clk_hw_busy_divider("ahb", "periph", base + 0x14, 10, 3, base + 0x48,… in imx6sl_clocks_init()
365 …K_MMDC_ROOT] = imx_clk_hw_busy_divider("mmdc", "periph2", base + 0x14, 3, 3, base + 0x48,… in imx6sl_clocks_init()
366 …K_ARM] = imx_clk_hw_busy_divider("arm", "pll1_sw", base + 0x10, 0, 3, base + 0x48,… in imx6sl_clocks_init()
[all …]
A Dclk-imx6ul.c129 void __iomem *base; in imx6ul_clocks_init() local
149 base = of_iomap(np, 0); in imx6ul_clocks_init()
151 WARN_ON(!base); in imx6ul_clocks_init()
246 base = of_iomap(np, 0); in imx6ul_clocks_init()
247 WARN_ON(!base); in imx6ul_clocks_init()
299 …hws[IMX6UL_CLK_PERIPH] = imx_clk_hw_busy_mux("periph", base + 0x14, 25, 1, base + 0x48, 5, perip… in imx6ul_clocks_init()
340 …hws[IMX6UL_CLK_ARM] = imx_clk_hw_busy_divider("arm", "pll1_sw", base + 0x10, 0, 3, base + 0… in imx6ul_clocks_init()
341 …K_MMDC_PODF] = imx_clk_hw_busy_divider("mmdc_podf", "periph2", base + 0x14, 3, 3, base + 0x48, … in imx6ul_clocks_init()
342 …LK_AXI_PODF] = imx_clk_hw_busy_divider("axi_podf", "axi_sel", base + 0x14, 16, 3, base + 0x48, … in imx6ul_clocks_init()
343 …hws[IMX6UL_CLK_AHB] = imx_clk_hw_busy_divider("ahb", "periph", base + 0x14, 10, 3, base + 0… in imx6ul_clocks_init()
[all …]
A Dclk-imx6sx.c123 void __iomem *base; in imx6sx_clocks_init() local
147 base = of_iomap(np, 0); in imx6sx_clocks_init()
148 WARN_ON(!base); in imx6sx_clocks_init()
219 base + 0xe0, 0, 2, 0, clk_enet_ref_table, in imx6sx_clocks_init()
222 base + 0xe0, 2, 2, 0, clk_enet_ref_table, in imx6sx_clocks_init()
261 base = of_iomap(np, 0); in imx6sx_clocks_init()
262 WARN_ON(!base); in imx6sx_clocks_init()
363 …] = imx_clk_hw_busy_divider("ocram_podf", "ocram_sel", base + 0x14, 16, 3, base + 0x48… in imx6sx_clocks_init()
364 … = imx_clk_hw_busy_divider("ahb", "periph", base + 0x14, 10, 3, base + 0x48… in imx6sx_clocks_init()
365 … = imx_clk_hw_busy_divider("mmdc_podf", "periph2", base + 0x14, 3, 3, base + 0x48… in imx6sx_clocks_init()
[all …]
A Dclk-imx8mq.c288 void __iomem *base; in imx8mq_clocks_probe() local
309 base = of_iomap(np, 0); in imx8mq_clocks_probe()
311 if (WARN_ON(!base)) in imx8mq_clocks_probe()
331 hws[IMX8MQ_ARM_PLL] = imx_clk_hw_frac_pll("arm_pll", "arm_pll_ref_div", base + 0x28); in imx8mq_clocks_probe()
332 hws[IMX8MQ_GPU_PLL] = imx_clk_hw_frac_pll("gpu_pll", "gpu_pll_ref_div", base + 0x18); in imx8mq_clocks_probe()
333 hws[IMX8MQ_VPU_PLL] = imx_clk_hw_frac_pll("vpu_pll", "vpu_pll_ref_div", base + 0x20); in imx8mq_clocks_probe()
397 base = devm_platform_ioremap_resource(pdev, 0); in imx8mq_clocks_probe()
398 if (WARN_ON(IS_ERR(base))) in imx8mq_clocks_probe()
399 return PTR_ERR(base); in imx8mq_clocks_probe()
447 hws[IMX8MQ_CLK_IPG_ROOT] = imx_clk_hw_divider2("ipg_root", "ahb", base + 0x9080, 0, 1); in imx8mq_clocks_probe()
[all …]
A Dclk-imx8mm.c303 void __iomem *base; in imx8mm_clocks_probe() local
323 base = of_iomap(np, 0); in imx8mm_clocks_probe()
325 if (WARN_ON(!base)) in imx8mm_clocks_probe()
395 hws[IMX8MM_CLK_CLKOUT1] = imx_clk_hw_gate("clkout1", "clkout1_div", base + 0x128, 8); in imx8mm_clocks_probe()
398 hws[IMX8MM_CLK_CLKOUT2] = imx_clk_hw_gate("clkout2", "clkout2_div", base + 0x128, 24); in imx8mm_clocks_probe()
401 base = devm_platform_ioremap_resource(pdev, 0); in imx8mm_clocks_probe()
402 if (WARN_ON(IS_ERR(base))) in imx8mm_clocks_probe()
403 return PTR_ERR(base); in imx8mm_clocks_probe()
451 hws[IMX8MM_CLK_IPG_ROOT] = imx_clk_hw_divider2("ipg_root", "ahb", base + 0x9080, 0, 1); in imx8mm_clocks_probe()
472 hws[IMX8MM_CLK_SAI1] = imx8m_clk_hw_composite("sai1", imx8mm_sai1_sels, base + 0xa580); in imx8mm_clocks_probe()
[all …]
A Dclk-imx8mn.c323 void __iomem *base; in imx8mn_clocks_probe() local
343 base = of_iomap(np, 0); in imx8mn_clocks_probe()
345 if (WARN_ON(!base)) { in imx8mn_clocks_probe()
416 hws[IMX8MN_CLK_CLKOUT1] = imx_clk_hw_gate("clkout1", "clkout1_div", base + 0x128, 8); in imx8mn_clocks_probe()
419 hws[IMX8MN_CLK_CLKOUT2] = imx_clk_hw_gate("clkout2", "clkout2_div", base + 0x128, 24); in imx8mn_clocks_probe()
422 base = devm_platform_ioremap_resource(pdev, 0); in imx8mn_clocks_probe()
423 if (WARN_ON(IS_ERR(base))) { in imx8mn_clocks_probe()
424 ret = PTR_ERR(base); in imx8mn_clocks_probe()
461 hws[IMX8MN_CLK_IPG_ROOT] = imx_clk_hw_divider2("ipg_root", "ahb", base + 0x9080, 0, 1); in imx8mn_clocks_probe()
474 hws[IMX8MN_CLK_SAI2] = imx8m_clk_hw_composite("sai2", imx8mn_sai2_sels, base + 0xa600); in imx8mn_clocks_probe()
[all …]
A Dclk-imx6q.c439 void __iomem *anatop_base, *base; in imx6q_clocks_init() local
461 anatop_base = base = of_iomap(np, 0); in imx6q_clocks_init()
462 WARN_ON(!base); in imx6q_clocks_init()
546 base + 0xe0, 0, 2, 0, clk_enet_ref_table, in imx6q_clocks_init()
569 writel(readl(base + 0x160) & ~0x3c00, base + 0x160); in imx6q_clocks_init()
607 base = of_iomap(np, 0); in imx6q_clocks_init()
608 WARN_ON(!base); in imx6q_clocks_init()
646 imx_mmdc_mask_handshake(base, 1); in imx6q_clocks_init()
657 init_ldb_clks(np, base); in imx6q_clocks_init()
783 … = imx_clk_hw_busy_divider("axi", "axi_sel", base + 0x14, 16, 3, base + 0x48,… in imx6q_clocks_init()
[all …]
A Dclk-imx7ulp.c50 void __iomem *base; in imx7ulp_clk_scg1_init() local
69 base = of_iomap(np, 0); in imx7ulp_clk_scg1_init()
70 WARN_ON(!base); in imx7ulp_clk_scg1_init()
139 void __iomem *base; in imx7ulp_clk_pcc2_init() local
150 base = of_iomap(np, 0); in imx7ulp_clk_pcc2_init()
151 WARN_ON(!base); in imx7ulp_clk_pcc2_init()
187 void __iomem *base; in imx7ulp_clk_pcc3_init() local
198 base = of_iomap(np, 0); in imx7ulp_clk_pcc3_init()
199 WARN_ON(!base); in imx7ulp_clk_pcc3_init()
234 void __iomem *base; in imx7ulp_clk_smc1_init() local
[all …]
/linux-6.3-rc2/drivers/gpu/drm/omapdrm/dss/
A Dhdmi5_core.c28 void __iomem *base = core->base; in hdmi5_core_ddc_init() local
107 void __iomem *base = core->base; in hdmi5_core_ddc_uninit() local
118 void __iomem *base = core->base; in hdmi5_core_ddc_read() local
275 void __iomem *base = core->base; in hdmi_core_video_config() local
337 void __iomem *base = core->base; in hdmi_core_config_video_packetizer() local
367 void __iomem *base = core->base; in hdmi_core_write_avi_infoframe() local
423 void __iomem *base = core->base; in hdmi_core_write_csc() local
485 void __iomem *base = core->base; in hdmi_core_enable_video_path() local
501 void __iomem *base = core->base; in hdmi_core_mask_interrupts() local
550 void __iomem *base = core->base; in hdmi5_core_handle_irqs() local
[all …]
/linux-6.3-rc2/drivers/scsi/
A Daha1740.h19 #define HID0(base) (base + 0x0) argument
20 #define HID1(base) (base + 0x1) argument
21 #define HID2(base) (base + 0x2) argument
22 #define HID3(base) (base + 0x3) argument
23 #define EBCNTRL(base) (base + 0x4) argument
24 #define PORTADR(base) (base + 0x40) argument
26 #define INTDEF(base) (base + 0x42) argument
28 #define BUSDEF(base) (base + 0x44) argument
29 #define RESV0(base) (base + 0x45) argument
30 #define RESV1(base) (base + 0x46) argument
[all …]
A Dnsp32_io.h16 outb(val, (base + index)); in nsp32_write1()
22 return inb(base + index); in nsp32_read1()
29 outw(val, (base + index)); in nsp32_write2()
35 return inw(base + index); in nsp32_read2()
42 outl(val, (base + index)); in nsp32_write4()
48 return inl(base + index); in nsp32_read4()
121 outb(reg, base + INDEX_REG); in nsp32_index_read1()
136 outb(reg, base + INDEX_REG); in nsp32_index_read2()
153 outb(reg, base + INDEX_REG); in nsp32_index_read4()
154 l = inw(base + DATA_REG_LOW); in nsp32_index_read4()
[all …]
/linux-6.3-rc2/drivers/video/fbdev/omap2/omapfb/dss/
A Dhdmi5_core.c41 void __iomem *base = core->base; in hdmi_core_ddc_init() local
120 void __iomem *base = core->base; in hdmi_core_ddc_uninit() local
130 void __iomem *base = core->base; in hdmi_core_ddc_edid() local
307 void __iomem *base = core->base; in hdmi_core_video_config() local
371 void __iomem *base = core->base; in hdmi_core_config_video_packetizer() local
409 void __iomem *base = core->base; in hdmi_core_write_avi_infoframe() local
465 void __iomem *base = core->base; in hdmi_core_csc_config() local
507 void __iomem *base = core->base; in hdmi_core_enable_video_path() local
523 void __iomem *base = core->base; in hdmi_core_mask_interrupts() local
572 void __iomem *base = core->base; in hdmi5_core_handle_irqs() local
[all …]
/linux-6.3-rc2/drivers/gpu/drm/sun4i/
A Dsun8i_vi_scaler.h30 #define SUN8I_SCALER_VSU_CTRL(base) ((base) + 0x0) argument
32 #define SUN50I_SCALER_VSU_DIR_THR(base) ((base) + 0x20) argument
36 #define SUN8I_SCALER_VSU_OUTSIZE(base) ((base) + 0x40) argument
37 #define SUN8I_SCALER_VSU_YINSIZE(base) ((base) + 0x80) argument
38 #define SUN8I_SCALER_VSU_YHSTEP(base) ((base) + 0x88) argument
39 #define SUN8I_SCALER_VSU_YVSTEP(base) ((base) + 0x8c) argument
40 #define SUN8I_SCALER_VSU_YHPHASE(base) ((base) + 0x90) argument
41 #define SUN8I_SCALER_VSU_YVPHASE(base) ((base) + 0x98) argument
42 #define SUN8I_SCALER_VSU_CINSIZE(base) ((base) + 0xc0) argument
43 #define SUN8I_SCALER_VSU_CHSTEP(base) ((base) + 0xc8) argument
[all …]
/linux-6.3-rc2/arch/mips/alchemy/common/
A Dusb.c159 __au1300_usb_phyctl(base, enable); in __au1300_ohci_control()
267 void __iomem *base = in au1300_usb_control() local
295 void __iomem *base = in au1300_usb_init() local
362 void __iomem *base = in au1200_usb_control() local
385 void __iomem *base = in au1200_usb_init() local
417 __raw_writel(r, base); in au1000_usb_init()
446 while (__raw_readl(base + creg), in __au1xx0_ohci_control()
519 __raw_writel(0, base + 0x04); in au1000_usb_pm()
521 __raw_writel(0, base + creg); in au1000_usb_pm()
531 void __iomem *base = in au1200_usb_pm() local
[all …]
/linux-6.3-rc2/drivers/media/platform/samsung/s5p-jpeg/
A Djpeg-hw-exynos4.c16 void exynos4_jpeg_sw_reset(void __iomem *base) in exynos4_jpeg_sw_reset() argument
20 reg = readl(base + EXYNOS4_JPEG_CNTL_REG); in exynos4_jpeg_sw_reset()
22 base + EXYNOS4_JPEG_CNTL_REG); in exynos4_jpeg_sw_reset()
24 reg = readl(base + EXYNOS4_JPEG_CNTL_REG); in exynos4_jpeg_sw_reset()
36 reg = readl(base + EXYNOS4_JPEG_CNTL_REG); in exynos4_jpeg_set_enc_dec_mode()
41 base + EXYNOS4_JPEG_CNTL_REG); in exynos4_jpeg_set_enc_dec_mode()
45 base + EXYNOS4_JPEG_CNTL_REG); in exynos4_jpeg_set_enc_dec_mode()
48 base + EXYNOS4_JPEG_CNTL_REG); in exynos4_jpeg_set_enc_dec_mode()
201 base + EXYNOS4_JPEG_CNTL_REG); in exynos4_jpeg_set_huf_table_enable()
204 base + EXYNOS4_JPEG_CNTL_REG); in exynos4_jpeg_set_huf_table_enable()
[all …]
/linux-6.3-rc2/drivers/phy/mediatek/
A Dphy-mtk-hdmi-mt2701.c53 void __iomem *base = hdmi_phy->regs; in mtk_hdmi_pll_prepare() local
55 mtk_phy_set_bits(base + HDMI_CON7, RG_HTPLL_AUTOK_EN); in mtk_hdmi_pll_prepare()
56 mtk_phy_clear_bits(base + HDMI_CON6, RG_HTPLL_RLH_EN); in mtk_hdmi_pll_prepare()
60 mtk_phy_set_bits(base + HDMI_CON6, RG_HTPLL_EN); in mtk_hdmi_pll_prepare()
75 void __iomem *base = hdmi_phy->regs; in mtk_hdmi_pll_unprepare() local
84 mtk_phy_clear_bits(base + HDMI_CON6, RG_HTPLL_EN); in mtk_hdmi_pll_unprepare()
103 void __iomem *base = hdmi_phy->regs; in mtk_hdmi_pll_set_rate() local
179 void __iomem *base = hdmi_phy->regs; in mtk_hdmi_phy_enable_tmds() local
186 mtk_phy_set_bits(base + HDMI_CON6, RG_HTPLL_EN); in mtk_hdmi_phy_enable_tmds()
199 void __iomem *base = hdmi_phy->regs; in mtk_hdmi_phy_disable_tmds() local
[all …]
/linux-6.3-rc2/drivers/net/ethernet/broadcom/bnx2x/
A Dbnx2x_fw_defs.h25 (IRO[163].base + ((funcId) * IRO[163].m1))
27 (IRO[153].base + ((funcId) * IRO[153].m1))
35 (IRO[324].base + ((pfId) * IRO[324].m1))
37 (IRO[325].base + ((pfId) * IRO[325].m1))
53 (IRO[323].base + ((pfId) * IRO[323].m1))
55 (IRO[315].base + ((pfId) * IRO[315].m1))
57 (IRO[314].base + ((pfId) * IRO[314].m1))
59 (IRO[313].base + ((pfId) * IRO[313].m1))
63 (IRO[146].base + ((pfId) * IRO[146].m1))
65 (IRO[147].base + ((pfId) * IRO[147].m1))
[all …]
/linux-6.3-rc2/tools/testing/memblock/tests/
A Dbasic_api.c57 ASSERT_EQ(rgn->base, r.base); in memblock_add_simple_check()
90 ASSERT_EQ(rgn->base, r.base); in memblock_add_node_simple_check()
139 ASSERT_EQ(rgn1->base, r1.base); in memblock_add_disjoint_check()
142 ASSERT_EQ(rgn2->base, r2.base); in memblock_add_disjoint_check()
194 ASSERT_EQ(rgn->base, r2.base); in memblock_add_overlap_top_check()
246 ASSERT_EQ(rgn->base, r1.base); in memblock_add_overlap_bottom_check()
293 ASSERT_EQ(rgn->base, r1.base); in memblock_add_within_check()
371 ASSERT_EQ(rgn->base, r1.base); in memblock_add_between_check()
415 ASSERT_EQ(rgn->base, r.base); in memblock_add_near_max_check()
562 ASSERT_EQ(rgn->base, r.base); in memblock_reserve_simple_check()
[all …]
/linux-6.3-rc2/drivers/gpu/drm/msm/dsi/phy/
A Ddsi_phy_20nm.c13 void __iomem *base = phy->base; in dsi_20nm_dphy_set_timing() local
15 dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_0, in dsi_20nm_dphy_set_timing()
17 dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_1, in dsi_20nm_dphy_set_timing()
19 dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_2, in dsi_20nm_dphy_set_timing()
22 dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_3, in dsi_20nm_dphy_set_timing()
24 dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_4, in dsi_20nm_dphy_set_timing()
26 dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_5, in dsi_20nm_dphy_set_timing()
28 dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_6, in dsi_20nm_dphy_set_timing()
30 dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_7, in dsi_20nm_dphy_set_timing()
45 void __iomem *base = phy->reg_base; in dsi_20nm_phy_regulator_ctrl() local
[all …]

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