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Searched refs:bw_ctx (Results 1 – 25 of 52) sorted by relevance

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/linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dml/dcn30/
A Ddcn30_fpu.c391 dcfclk = context->bw_ctx.dml.soc.min_dcfclk; in dcn30_fpu_calculate_wm_and_dlg()
410 …context->bw_ctx.bw.dcn.watermarks.b.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cn… in dcn30_fpu_calculate_wm_and_dlg()
414 …context->bw_ctx.bw.dcn.watermarks.b.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, … in dcn30_fpu_calculate_wm_and_dlg()
417 …context->bw_ctx.bw.dcn.watermarks.b.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, p… in dcn30_fpu_calculate_wm_and_dlg()
466 …context->bw_ctx.bw.dcn.watermarks.c.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cn… in dcn30_fpu_calculate_wm_and_dlg()
470 …context->bw_ctx.bw.dcn.watermarks.c.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, … in dcn30_fpu_calculate_wm_and_dlg()
473 …context->bw_ctx.bw.dcn.watermarks.c.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, p… in dcn30_fpu_calculate_wm_and_dlg()
479 context->bw_ctx.bw.dcn.watermarks.a = context->bw_ctx.bw.dcn.watermarks.c; in dcn30_fpu_calculate_wm_and_dlg()
489 …context->bw_ctx.bw.dcn.watermarks.a.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cn… in dcn30_fpu_calculate_wm_and_dlg()
496 …context->bw_ctx.bw.dcn.watermarks.a.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, p… in dcn30_fpu_calculate_wm_and_dlg()
[all …]
/linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dml/dcn32/
A Ddcn32_fpu.c378 context->bw_ctx.dml.soc.clock_limits[context->bw_ctx.dml.soc.num_states - 1].dispclk_mhz, in dcn32_predict_pipe_split()
379 context->bw_ctx.dml.soc.clock_limits[context->bw_ctx.dml.soc.num_states - 1].dispclk_mhz, in dcn32_predict_pipe_split()
1324 context->bw_ctx.bw.dcn.clk.dispclk_khz = context->bw_ctx.dml.vba.DISPCLK * 1000; in dcn32_calculate_dlg_params()
1325 context->bw_ctx.bw.dcn.clk.dcfclk_khz = context->bw_ctx.dml.vba.DCFCLK * 1000; in dcn32_calculate_dlg_params()
1326 context->bw_ctx.bw.dcn.clk.socclk_khz = context->bw_ctx.dml.vba.SOCCLK * 1000; in dcn32_calculate_dlg_params()
1327 context->bw_ctx.bw.dcn.clk.dramclk_khz = context->bw_ctx.dml.vba.DRAMSpeed * 1000 / 16; in dcn32_calculate_dlg_params()
1329 context->bw_ctx.bw.dcn.clk.fclk_khz = context->bw_ctx.dml.vba.FabricClock * 1000; in dcn32_calculate_dlg_params()
1432 context->bw_ctx.bw.dcn.clk.bw_dppclk_khz = context->bw_ctx.bw.dcn.clk.dppclk_khz; in dcn32_calculate_dlg_params()
1433 context->bw_ctx.bw.dcn.clk.bw_dispclk_khz = context->bw_ctx.bw.dcn.clk.dispclk_khz; in dcn32_calculate_dlg_params()
1453 context->bw_ctx.dml.funcs.rq_dlg_get_dlg_reg_v2(&context->bw_ctx.dml, in dcn32_calculate_dlg_params()
[all …]
/linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dml/dcn31/
A Ddcn31_fpu.c469 …if (context->bw_ctx.dml.vba.DRAMClockChangeSupport[context->bw_ctx.dml.vba.VoltageLevel][context->… in dcn315_update_soc_for_wm_a()
470 …context->bw_ctx.dml.soc.dram_clock_change_latency_us = context->bw_ctx.dml.soc.dummy_pstate_latenc… in dcn315_update_soc_for_wm_a()
475 context->bw_ctx.dml.soc.sr_exit_time_us = in dcn315_update_soc_for_wm_a()
487 double dcfclk = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb]; in dcn31_calculate_wm_and_dlg_fp()
513 …context->bw_ctx.bw.dcn.watermarks.a.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cn… in dcn31_calculate_wm_and_dlg_fp()
523 context->bw_ctx.bw.dcn.watermarks.b = context->bw_ctx.bw.dcn.watermarks.a; in dcn31_calculate_wm_and_dlg_fp()
524 context->bw_ctx.bw.dcn.watermarks.c = context->bw_ctx.bw.dcn.watermarks.a; in dcn31_calculate_wm_and_dlg_fp()
525 context->bw_ctx.bw.dcn.watermarks.d = context->bw_ctx.bw.dcn.watermarks.a; in dcn31_calculate_wm_and_dlg_fp()
555 context->bw_ctx.bw.dcn.clk.socclk_khz = 0; in dcn31_calculate_wm_and_dlg_fp()
556 context->bw_ctx.bw.dcn.clk.dppclk_khz = 0; in dcn31_calculate_wm_and_dlg_fp()
[all …]
/linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dml/dcn20/
A Ddcn20_fpu.c1052 context->bw_ctx.bw.dcn.clk.dispclk_khz = context->bw_ctx.dml.vba.DISPCLK * 1000; in dcn20_calculate_dlg_params()
1053 context->bw_ctx.bw.dcn.clk.dcfclk_khz = context->bw_ctx.dml.vba.DCFCLK * 1000; in dcn20_calculate_dlg_params()
1054 context->bw_ctx.bw.dcn.clk.socclk_khz = context->bw_ctx.dml.vba.SOCCLK * 1000; in dcn20_calculate_dlg_params()
1055 context->bw_ctx.bw.dcn.clk.dramclk_khz = context->bw_ctx.dml.vba.DRAMSpeed * 1000 / 16; in dcn20_calculate_dlg_params()
1060 context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz = context->bw_ctx.dml.vba.DCFCLKDeepSleep * 1000; in dcn20_calculate_dlg_params()
1061 context->bw_ctx.bw.dcn.clk.fclk_khz = context->bw_ctx.dml.vba.FabricClock * 1000; in dcn20_calculate_dlg_params()
1063 context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] in dcn20_calculate_dlg_params()
1106 context->bw_ctx.bw.dcn.clk.bw_dppclk_khz = context->bw_ctx.bw.dcn.clk.dppclk_khz; in dcn20_calculate_dlg_params()
1107 context->bw_ctx.bw.dcn.clk.bw_dispclk_khz = context->bw_ctx.bw.dcn.clk.dispclk_khz; in dcn20_calculate_dlg_params()
1123 context->bw_ctx.dml.funcs.rq_dlg_get_dlg_reg(&context->bw_ctx.dml, in dcn20_calculate_dlg_params()
[all …]
/linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/core/
A Ddc_debug.c351 context->bw_ctx.bw.dcn.clk.dispclk_khz, in context_clock_trace()
352 context->bw_ctx.bw.dcn.clk.dppclk_khz, in context_clock_trace()
353 context->bw_ctx.bw.dcn.clk.dcfclk_khz, in context_clock_trace()
354 context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz, in context_clock_trace()
355 context->bw_ctx.bw.dcn.clk.fclk_khz, in context_clock_trace()
356 context->bw_ctx.bw.dcn.clk.socclk_khz); in context_clock_trace()
359 context->bw_ctx.bw.dcn.clk.dispclk_khz, in context_clock_trace()
360 context->bw_ctx.bw.dcn.clk.dppclk_khz, in context_clock_trace()
361 context->bw_ctx.bw.dcn.clk.dcfclk_khz, in context_clock_trace()
363 context->bw_ctx.bw.dcn.clk.fclk_khz, in context_clock_trace()
[all …]
A Ddc.c1897 TRACE_DCN_CLOCK_STATE(&context->bw_ctx.bw.dcn.clk); in dc_commit_state_no_check()
1899 TRACE_DCE_CLOCK_STATE(&context->bw_ctx.bw.dce); in dc_commit_state_no_check()
2138 TRACE_DCN_CLOCK_STATE(&context->bw_ctx.bw.dcn.clk); in dc_post_update_surfaces_to_stream()
2140 TRACE_DCE_CLOCK_STATE(&context->bw_ctx.bw.dce); in dc_post_update_surfaces_to_stream()
2169 memcpy(&context->bw_ctx.dml, &dc->dml, sizeof(struct display_mode_lib)); in init_state()
4194 TRACE_DCE_CLOCK_STATE(&context->bw_ctx.bw.dce); in dc_commit_updates_for_stream()
4295 dc->current_state->bw_ctx.dml = *dml; in dc_set_power_state()
4477 info->dppClock = (unsigned int)state->bw_ctx.bw.dcn.clk.dppclk_khz; in get_clock_requirements_for_state()
4478 info->socClock = (unsigned int)state->bw_ctx.bw.dcn.clk.socclk_khz; in get_clock_requirements_for_state()
4480 info->fClock = (unsigned int)state->bw_ctx.bw.dcn.clk.fclk_khz; in get_clock_requirements_for_state()
[all …]
/linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dce112/
A Ddce112_resource.c901 &context->bw_ctx.bw.dce)) in dce112_validate_bandwidth()
909 if (memcmp(&dc->current_state->bw_ctx.bw.dce, in dce112_validate_bandwidth()
910 &context->bw_ctx.bw.dce, sizeof(context->bw_ctx.bw.dce))) { in dce112_validate_bandwidth()
926 context->bw_ctx.bw.dce.urgent_wm_ns[0].b_mark, in dce112_validate_bandwidth()
927 context->bw_ctx.bw.dce.urgent_wm_ns[0].a_mark, in dce112_validate_bandwidth()
942 context->bw_ctx.bw.dce.stutter_mode_enable, in dce112_validate_bandwidth()
946 context->bw_ctx.bw.dce.all_displays_in_sync, in dce112_validate_bandwidth()
947 context->bw_ctx.bw.dce.dispclk_khz, in dce112_validate_bandwidth()
948 context->bw_ctx.bw.dce.sclk_khz, in dce112_validate_bandwidth()
949 context->bw_ctx.bw.dce.sclk_deep_sleep_khz, in dce112_validate_bandwidth()
[all …]
/linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/
A Ddce110_clk_mgr.c183 context->bw_ctx.bw.dce.all_displays_in_sync; in dce11_pplib_apply_display_requirements()
185 context->bw_ctx.bw.dce.nbp_state_change_enable == false; in dce11_pplib_apply_display_requirements()
187 context->bw_ctx.bw.dce.cpuc_state_change_enable == false; in dce11_pplib_apply_display_requirements()
189 context->bw_ctx.bw.dce.cpup_state_change_enable == false; in dce11_pplib_apply_display_requirements()
191 context->bw_ctx.bw.dce.blackout_recovery_time_us; in dce11_pplib_apply_display_requirements()
205 pp_display_cfg->min_memory_clock_khz = context->bw_ctx.bw.dce.yclk_khz in dce11_pplib_apply_display_requirements()
211 context->bw_ctx.bw.dce.sclk_khz); in dce11_pplib_apply_display_requirements()
224 = context->bw_ctx.bw.dce.sclk_deep_sleep_khz; in dce11_pplib_apply_display_requirements()
255 int patched_disp_clk = context->bw_ctx.bw.dce.dispclk_khz; in dce11_update_clocks()
270 context->bw_ctx.bw.dce.dispclk_khz = dce_set_clock(clk_mgr_base, patched_disp_clk); in dce11_update_clocks()
/linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dml/calcs/
A Ddcn_calcs.c630 context->bw_ctx.bw.dcn.watermarks.b = context->bw_ctx.bw.dcn.watermarks.a;
631 context->bw_ctx.bw.dcn.watermarks.c = context->bw_ctx.bw.dcn.watermarks.a;
634 context->bw_ctx.bw.dcn.watermarks.d = context->bw_ctx.bw.dcn.watermarks.a;
1153 context->bw_ctx.bw.dcn.watermarks.b = context->bw_ctx.bw.dcn.watermarks.a; in dcn_validate_bandwidth()
1154 context->bw_ctx.bw.dcn.watermarks.c = context->bw_ctx.bw.dcn.watermarks.a; in dcn_validate_bandwidth()
1155 context->bw_ctx.bw.dcn.watermarks.d = context->bw_ctx.bw.dcn.watermarks.a; in dcn_validate_bandwidth()
1169 if (context->bw_ctx.bw.dcn.clk.dispclk_khz < in dcn_validate_bandwidth()
1171 context->bw_ctx.bw.dcn.clk.dispclk_khz = in dcn_validate_bandwidth()
1175 context->bw_ctx.bw.dcn.clk.dppclk_khz = context->bw_ctx.bw.dcn.clk.dispclk_khz / in dcn_validate_bandwidth()
1180 context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz = in dcn_validate_bandwidth()
[all …]
/linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dce110/
A Ddce110_resource.c979 &context->bw_ctx.bw.dce)) in dce110_validate_bandwidth()
989 if (memcmp(&dc->current_state->bw_ctx.bw.dce, in dce110_validate_bandwidth()
990 &context->bw_ctx.bw.dce, sizeof(context->bw_ctx.bw.dce))) { in dce110_validate_bandwidth()
1006 context->bw_ctx.bw.dce.urgent_wm_ns[0].b_mark, in dce110_validate_bandwidth()
1007 context->bw_ctx.bw.dce.urgent_wm_ns[0].a_mark, in dce110_validate_bandwidth()
1022 context->bw_ctx.bw.dce.stutter_mode_enable, in dce110_validate_bandwidth()
1026 context->bw_ctx.bw.dce.all_displays_in_sync, in dce110_validate_bandwidth()
1027 context->bw_ctx.bw.dce.dispclk_khz, in dce110_validate_bandwidth()
1028 context->bw_ctx.bw.dce.sclk_khz, in dce110_validate_bandwidth()
1029 context->bw_ctx.bw.dce.sclk_deep_sleep_khz, in dce110_validate_bandwidth()
[all …]
/linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dml/dcn301/
A Ddcn301_fpu.c436 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.d, in dcn301_calculate_wm_and_dlg_fp()
437 &context->bw_ctx.dml, pipes, pipe_cnt); in dcn301_calculate_wm_and_dlg_fp()
441 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.c, in dcn301_calculate_wm_and_dlg_fp()
442 &context->bw_ctx.dml, pipes, pipe_cnt); in dcn301_calculate_wm_and_dlg_fp()
446 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.b, in dcn301_calculate_wm_and_dlg_fp()
447 &context->bw_ctx.dml, pipes, pipe_cnt); in dcn301_calculate_wm_and_dlg_fp()
452 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.a, in dcn301_calculate_wm_and_dlg_fp()
453 &context->bw_ctx.dml, pipes, pipe_cnt); in dcn301_calculate_wm_and_dlg_fp()
459 …pipes[pipe_idx].clks_cfg.dispclk_mhz = get_dispclk_calculated(&context->bw_ctx.dml, pipes, pipe_cn… in dcn301_calculate_wm_and_dlg_fp()
463 pipes[pipe_idx].clks_cfg.dispclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dispclk_mhz; in dcn301_calculate_wm_and_dlg_fp()
[all …]
/linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dce/
A Ddce_clk_mgr.c227 if (context->bw_ctx.bw.dce.dispclk_khz > in dce_get_required_clocks_state()
237 < context->bw_ctx.bw.dce.dispclk_khz) in dce_get_required_clocks_state()
619 context->bw_ctx.bw.dce.all_displays_in_sync; in dce11_pplib_apply_display_requirements()
621 context->bw_ctx.bw.dce.nbp_state_change_enable == false; in dce11_pplib_apply_display_requirements()
627 context->bw_ctx.bw.dce.blackout_recovery_time_us; in dce11_pplib_apply_display_requirements()
634 context->bw_ctx.bw.dce.sclk_khz); in dce11_pplib_apply_display_requirements()
647 = context->bw_ctx.bw.dce.sclk_deep_sleep_khz; in dce11_pplib_apply_display_requirements()
678 int patched_disp_clk = context->bw_ctx.bw.dce.dispclk_khz; in dce_update_clocks()
705 int patched_disp_clk = context->bw_ctx.bw.dce.dispclk_khz; in dce11_update_clocks()
732 int patched_disp_clk = context->bw_ctx.bw.dce.dispclk_khz; in dce112_update_clocks()
[all …]
/linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dml/dcn314/
A Ddcn314_fpu.c346 context->bw_ctx.dml.ip.det_buffer_size_kbytes = DCN3_14_DEFAULT_DET_SIZE; in dcn314_populate_dml_pipes_from_context_fpu()
356 context->bw_ctx.dml.ip.det_buffer_size_kbytes = 192; in dcn314_populate_dml_pipes_from_context_fpu()
361 context->bw_ctx.dml.ip.det_buffer_size_kbytes = dc->debug.crb_alloc_policy * 64; in dcn314_populate_dml_pipes_from_context_fpu()
363 context->bw_ctx.dml.ip.det_buffer_size_kbytes = 192; in dcn314_populate_dml_pipes_from_context_fpu()
376 context->bw_ctx.dml.vba.ODMCombinePolicy = dm_odm_combine_policy_2to1; in dcn314_populate_dml_pipes_from_context_fpu()
/linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dcn30/
A Ddcn30_resource.c1398 struct display_mode_lib *dml = &context->bw_ctx.dml; in dcn30_set_mcif_arb_params()
1660 struct vba_vars_st *vba = &context->bw_ctx.dml.vba; in dcn30_internal_validate_bw()
1666 context->bw_ctx.dml.vba.maxMpcComb = 0; in dcn30_internal_validate_bw()
1667 context->bw_ctx.dml.vba.VoltageLevel = 0; in dcn30_internal_validate_bw()
1677 dml_log_pipe_params(&context->bw_ctx.dml, pipes, pipe_cnt); in dcn30_internal_validate_bw()
1689 if (vlevel < context->bw_ctx.dml.soc.num_states) in dcn30_internal_validate_bw()
1706 if (vlevel < context->bw_ctx.dml.soc.num_states) { in dcn30_internal_validate_bw()
1713 dml_log_mode_support_params(&context->bw_ctx.dml); in dcn30_internal_validate_bw()
1715 if (vlevel == context->bw_ctx.dml.soc.num_states) in dcn30_internal_validate_bw()
1888 context->bw_ctx.dml.vba.VoltageLevel = vlevel; in dcn30_internal_validate_bw()
[all …]
/linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dcn21/
A Ddcn21_resource.c842 context->bw_ctx.dml.soc.allow_dram_self_refresh_or_dram_clock_change_in_vblank = in dcn21_fast_validate_bw()
844 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt); in dcn21_fast_validate_bw()
846 if (vlevel > context->bw_ctx.dml.soc.num_states) { in dcn21_fast_validate_bw()
854 context->bw_ctx.dml.soc.allow_dram_self_refresh_or_dram_clock_change_in_vblank = in dcn21_fast_validate_bw()
856 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt); in dcn21_fast_validate_bw()
857 if (vlevel > context->bw_ctx.dml.soc.num_states) in dcn21_fast_validate_bw()
866 struct vba_vars_st *vba = &context->bw_ctx.dml.vba; in dcn21_fast_validate_bw()
896 …if (!pipe->top_pipe && !pipe->plane_state && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) { in dcn21_fast_validate_bw()
920 …dcn20_fpu_adjust_dppclk(&context->bw_ctx.dml.vba, vlevel, context->bw_ctx.dml.vba.maxMpcComb, pipe… in dcn21_fast_validate_bw()
924 if (context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) { in dcn21_fast_validate_bw()
[all …]
/linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dcn10/
A Ddcn10_hw_sequencer_debug.c475 dc->current_state->bw_ctx.bw.dcn.clk.dcfclk_khz, in dcn10_get_clock_states()
476 dc->current_state->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz, in dcn10_get_clock_states()
477 dc->current_state->bw_ctx.bw.dcn.clk.dispclk_khz, in dcn10_get_clock_states()
478 dc->current_state->bw_ctx.bw.dcn.clk.dppclk_khz, in dcn10_get_clock_states()
479 dc->current_state->bw_ctx.bw.dcn.clk.fclk_khz, in dcn10_get_clock_states()
480 dc->current_state->bw_ctx.bw.dcn.clk.socclk_khz); in dcn10_get_clock_states()
A Ddcn10_hw_sequencer.c463 dc->current_state->bw_ctx.bw.dcn.clk.dcfclk_khz, in dcn10_log_hw_state()
465 dc->current_state->bw_ctx.bw.dcn.clk.dispclk_khz, in dcn10_log_hw_state()
466 dc->current_state->bw_ctx.bw.dcn.clk.dppclk_khz, in dcn10_log_hw_state()
468 dc->current_state->bw_ctx.bw.dcn.clk.fclk_khz, in dcn10_log_hw_state()
469 dc->current_state->bw_ctx.bw.dcn.clk.socclk_khz); in dcn10_log_hw_state()
2749 if (context->bw_ctx.bw.dcn.clk.dispclk_khz < in dcn10_update_dchubp_dpp()
2754 context->bw_ctx.bw.dcn.clk.dppclk_khz <= in dcn10_update_dchubp_dpp()
3073 context->bw_ctx.bw.dcn.clk.phyclk_khz = 0; in dcn10_prepare_bandwidth()
3082 &context->bw_ctx.bw.dcn.watermarks, in dcn10_prepare_bandwidth()
3113 context->bw_ctx.bw.dcn.clk.phyclk_khz = 0; in dcn10_optimize_bandwidth()
[all …]
/linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/
A Ddcn20_clk_mgr.c221 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk; in dcn2_update_clocks()
349 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk; in dcn2_update_clocks_fpga()
456 clock_cfg->max_clock_khz = context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz; in dcn2_get_clock()
459 clock_cfg->bw_requirequired_clock_khz = context->bw_ctx.bw.dcn.clk.bw_dispclk_khz; in dcn2_get_clock()
462 clock_cfg->max_clock_khz = context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz; in dcn2_get_clock()
465 clock_cfg->bw_requirequired_clock_khz = context->bw_ctx.bw.dcn.clk.bw_dppclk_khz; in dcn2_get_clock()
/linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/
A Ddce_clk_mgr.c208 if (context->bw_ctx.bw.dce.dispclk_khz > in dce_get_required_clocks_state()
218 < context->bw_ctx.bw.dce.dispclk_khz) in dce_get_required_clocks_state()
403 int patched_disp_clk = context->bw_ctx.bw.dce.dispclk_khz; in dce_update_clocks()
/linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dcn20/
A Ddcn20_resource.c1649 wb_arb_params = &context->bw_ctx.bw.dcn.bw_writeback.mcif_wb_arb[dwb_pipe]; in dcn20_set_mcif_arb_params()
1862 struct vba_vars_st *v = &context->bw_ctx.dml.vba; in dcn20_validate_apply_pipe_split_flags()
1917 for (vlevel_split = vlevel; vlevel <= context->bw_ctx.dml.soc.num_states; vlevel++) in dcn20_validate_apply_pipe_split_flags()
1922 if (vlevel > context->bw_ctx.dml.soc.num_states) in dcn20_validate_apply_pipe_split_flags()
2069 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt); in dcn20_fast_validate_bw()
2071 if (vlevel > context->bw_ctx.dml.soc.num_states) in dcn20_fast_validate_bw()
2089 …if (!pipe->top_pipe && !pipe->plane_state && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) { in dcn20_fast_validate_bw()
2108 && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) in dcn20_fast_validate_bw()
2118 …dcn20_fpu_adjust_dppclk(&context->bw_ctx.dml.vba, vlevel, context->bw_ctx.dml.vba.maxMpcComb, pipe… in dcn20_fast_validate_bw()
2122 if (context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) { in dcn20_fast_validate_bw()
[all …]
A Ddcn20_hwseq.c2018 unsigned int cache_wm_a = context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns; in dcn20_prepare_bandwidth()
2031 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = 4U * 1000U * 1000U * 1000U; in dcn20_prepare_bandwidth()
2041 &context->bw_ctx.bw.dcn.watermarks, in dcn20_prepare_bandwidth()
2047 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = cache_wm_a; in dcn20_prepare_bandwidth()
2051 if (context->bw_ctx.dml.ip.min_comp_buffer_size_kbytes) { in dcn20_prepare_bandwidth()
2052 compbuf_size_kb = context->bw_ctx.dml.ip.min_comp_buffer_size_kbytes; in dcn20_prepare_bandwidth()
2055 compbuf_size_kb = context->bw_ctx.bw.dcn.compbuf_size_kb; in dcn20_prepare_bandwidth()
2075 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = 4U * 1000U * 1000U * 1000U; in dcn20_optimize_bandwidth()
2082 &context->bw_ctx.bw.dcn.watermarks, in dcn20_optimize_bandwidth()
2088 context->bw_ctx.bw.dcn.clk.dramclk_khz <= dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000) in dcn20_optimize_bandwidth()
[all …]
/linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/clk_mgr/dce120/
A Ddce120_clk_mgr.c91 int patched_disp_clk = context->bw_ctx.bw.dce.dispclk_khz; in dce12_update_clocks()
/linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/
A Ddce60_clk_mgr.c126 int patched_disp_clk = context->bw_ctx.bw.dce.dispclk_khz; in dce60_update_clocks()
/linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dcn32/
A Ddcn32_resource_helpers.c117 if (context->bw_ctx.bw.dcn.mall_subvp_size_bytes > 0) { in dcn32_helper_calculate_num_ways_for_subvp()
121 return dcn32_helper_mall_bytes_to_ways(dc, context->bw_ctx.bw.dcn.mall_subvp_size_bytes); in dcn32_helper_calculate_num_ways_for_subvp()
/linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dce100/
A Ddce100_resource.c850 context->bw_ctx.bw.dce.dispclk_khz = 681000; in dce100_validate_bandwidth()
851 context->bw_ctx.bw.dce.yclk_khz = 250000 * MEMORY_TYPE_MULTIPLIER_CZ; in dce100_validate_bandwidth()
853 context->bw_ctx.bw.dce.dispclk_khz = 0; in dce100_validate_bandwidth()
854 context->bw_ctx.bw.dce.yclk_khz = 0; in dce100_validate_bandwidth()

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