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/linux-6.3-rc2/arch/arm/mm/
A Dtlb-v7.S49 ALT_SMP(mcr p15, 0, r0, c8, c3, 3) @ TLB invalidate U MVA all ASID (shareable)
51 ALT_SMP(mcr p15, 0, r0, c8, c3, 1) @ TLB invalidate U MVA (shareable)
53 ALT_UP(mcr p15, 0, r0, c8, c7, 1) @ TLB invalidate U MVA
78 ALT_SMP(mcr p15, 0, r0, c8, c3, 3) @ TLB invalidate U MVA all ASID (shareable)
80 ALT_SMP(mcr p15, 0, r0, c8, c3, 1) @ TLB invalidate U MVA (shareable)
82 ALT_UP(mcr p15, 0, r0, c8, c7, 1) @ TLB invalidate U MVA
A Dtlb-v6.S48 mcr p15, 0, r0, c8, c6, 1 @ TLB invalidate D MVA (was 1)
50 mcrne p15, 0, r0, c8, c5, 1 @ TLB invalidate I MVA (was 1)
52 mcr p15, 0, r0, c8, c7, 1 @ TLB invalidate MVA (was 1)
77 mcr p15, 0, r0, c8, c6, 1 @ TLB invalidate D MVA
78 mcr p15, 0, r0, c8, c5, 1 @ TLB invalidate I MVA
80 mcr p15, 0, r0, c8, c7, 1 @ TLB invalidate MVA
A Dtlb-v4wb.S38 mcrne p15, 0, r3, c8, c5, 0 @ invalidate I TLB
41 1: mcr p15, 0, r0, c8, c6, 1 @ invalidate D TLB entry
61 mcr p15, 0, r3, c8, c5, 0 @ invalidate I TLB
62 1: mcr p15, 0, r0, c8, c6, 1 @ invalidate D TLB entry
A Dtlb-v4wbi.S40 mcrne p15, 0, r0, c8, c5, 1 @ invalidate I TLB entry
41 mcr p15, 0, r0, c8, c6, 1 @ invalidate D TLB entry
52 1: mcr p15, 0, r0, c8, c5, 1 @ invalidate I TLB entry
53 mcr p15, 0, r0, c8, c6, 1 @ invalidate D TLB entry
A Dproc-arm720.S68 mcr p15, 0, r1, c8, c7, 0 @ flush TLB (v4)
95 mcr p15, 0, ip, c8, c7, 0 @ flush TLB (v4)
110 mcr p15, 0, r0, c8, c7, 0 @ flush TLB (v4)
138 mcr p15, 0, r0, c8, c7, 0 @ flush TLB (v4)
A Dproc-sa110.S68 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
98 mcr p15, 0, r0, c15, c8, 2 @ Wait for interrupt, cache aligned
138 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
165 mcr p15, 0, r10, c8, c7 @ invalidate I,D TLBs on v4
A Dproc-sa1100.S76 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
110 mcr p15, 0, r0, c15, c8, 2 @ wait for interrupt
149 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
185 mcr p15, 0, ip, c8, c7, 0 @ flush I+D TLBs
204 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
A Dtlb-fa.S43 1: mcr p15, 0, r0, c8, c7, 1 @ invalidate UTLB entry
56 1: mcr p15, 0, r0, c8, c7, 1 @ invalidate UTLB entry
A Dproc-fa526.S61 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
113 mcr p15, 0, ip, c8, c7, 0 @ invalidate UTLB
140 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
A Dproc-mohawk.S64 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
322 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
362 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
380 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs
A Dproc-arm920.S80 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
354 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
388 mcr p15, 0, ip, c8, c7, 0 @ invalidate I+D TLBs
405 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
A Dtlb-v4.S38 1: mcr p15, 0, r0, c8, c7, 1 @ invalidate TLB entry
A Dproc-arm926.S72 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
367 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
403 mcr p15, 0, ip, c8, c7, 0 @ invalidate I+D TLBs
420 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
A Dproc-xscale.S148 mcr p15, 0, r1, c8, c5, 0 @ invalidate I-TLB
160 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
476 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
546 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
563 mcr p15, 0, ip, c8, c7, 0 @ invalidate I, D TLBs
A Dproc-arm1020e.S88 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
392 mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs
418 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
A Dproc-arm1022.S88 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
385 mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs
411 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
A Dproc-arm1026.S88 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
374 mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs
400 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
A Dproc-arm922.S82 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
358 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
383 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
A Dproc-xsc3.S118 mcr p15, 0, ip, c8, c7, 0 @ invalidate I and D TLBs
367 mcr p15, 0, ip, c8, c7, 0 @ invalidate I and D TLBs
433 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
453 mcr p15, 0, ip, c8, c7, 0 @ invalidate I and D TLBs
A Dproc-arm1020.S88 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
408 mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs
436 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
/linux-6.3-rc2/arch/arm/include/asm/hardware/
A Dcp14.h65 #define RCP14_DBGBVR8() MRC14(0, c0, c8, 4)
81 #define RCP14_DBGBCR8() MRC14(0, c0, c8, 5)
97 #define RCP14_DBGWVR8() MRC14(0, c0, c8, 6)
113 #define RCP14_DBGWCR8() MRC14(0, c0, c8, 7)
130 #define RCP14_DBGBXVR8() MRC14(0, c1, c8, 1)
281 #define RCP14_ETMTEEVR() MRC14(1, c0, c8, 0)
297 #define RCP14_ETMACVR8() MRC14(1, c0, c8, 1)
313 #define RCP14_ETMACTR8() MRC14(1, c0, c8, 2)
325 #define RCP14_ETMDCVR8() MRC14(1, c0, c8, 3)
333 #define RCP14_ETMDCMR8() MRC14(1, c0, c8, 4)
[all …]
/linux-6.3-rc2/arch/alpha/include/asm/
A Dstring.h39 unsigned long c8 = (c & 0xff) * 0x0101010101010101UL; in __memset() local
40 return __constant_c_memset(s, c8, n); in __memset()
/linux-6.3-rc2/arch/powerpc/crypto/
A Daes-tab-4k.S76 .long R(79, b1, b1, c8), R(b6, 5b, 5b, ed)
103 .long R(c8, 64, 64, ac), R(ba, 5d, 5d, e7)
121 .long R(d5, e7, e7, 32), R(8b, c8, c8, 43)
179 .long R(49, e0, 69, 29), R(8e, c9, c8, 44)
211 .long R(e7, 19, 5b, 38), R(79, c8, ee, db)
227 .long R(2d, b6, a8, b9), R(14, 1e, a9, c8)
254 .long R(c8, ac, 99, 3b), R(10, 18, 7d, a7)
/linux-6.3-rc2/tools/perf/arch/s390/include/
A Ddwarf-regs-table.h38 REG_DWARFNUM_NAME(c8, 40),
/linux-6.3-rc2/arch/arm/kernel/
A Dhead-nommu.S351 AR_CLASS(mcr p15, 0, r5, c6, c8, 0) @ PRBAR0
352 AR_CLASS(mcr p15, 0, r6, c6, c8, 1) @ PRLAR0
365 AR_CLASS(mcr p15, 0, r5, c6, c8, 4) @ PRBAR1
366 AR_CLASS(mcr p15, 0, r6, c6, c8, 5) @ PRLAR1

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