Searched refs:cdclk_state (Results 1 – 8 of 8) sorted by relevance
2512 cdclk_state->bw_min_cdclk); in intel_compute_min_cdclk()2598 cdclk_state->actual = cdclk_state->logical; in vlv_modeset_calc_cdclk()2625 cdclk_state->actual = cdclk_state->logical; in bdw_modeset_calc_cdclk()2693 cdclk_state->actual = cdclk_state->logical; in skl_modeset_calc_cdclk()2731 cdclk_state->actual = cdclk_state->logical; in bxt_modeset_calc_cdclk()2757 cdclk_state = kmemdup(obj->state, sizeof(*cdclk_state), GFP_KERNEL); in intel_cdclk_duplicate_state()2758 if (!cdclk_state) in intel_cdclk_duplicate_state()2763 return &cdclk_state->base; in intel_cdclk_duplicate_state()2784 if (IS_ERR(cdclk_state)) in intel_atomic_get_cdclk_state()2829 cdclk_state = kzalloc(sizeof(*cdclk_state), GFP_KERNEL); in intel_cdclk_init()[all …]
235 const struct intel_cdclk_state *cdclk_state; in hsw_ips_compute_config() local237 cdclk_state = intel_atomic_get_cdclk_state(state); in hsw_ips_compute_config()238 if (IS_ERR(cdclk_state)) in hsw_ips_compute_config()239 return PTR_ERR(cdclk_state); in hsw_ips_compute_config()242 if (crtc_state->pixel_rate > cdclk_state->logical.cdclk * 95 / 100) in hsw_ips_compute_config()
36 struct intel_cdclk_state *cdclk_state = in intel_crtc_disable_noatomic() local103 cdclk_state->min_cdclk[pipe] = 0; in intel_crtc_disable_noatomic()104 cdclk_state->min_voltage_level[pipe] = 0; in intel_crtc_disable_noatomic()105 cdclk_state->active_pipes &= ~BIT(pipe); in intel_crtc_disable_noatomic()433 struct intel_cdclk_state *cdclk_state = in intel_modeset_readout_hw_state() local468 cdclk_state->active_pipes = active_pipes; in intel_modeset_readout_hw_state()612 cdclk_state->min_cdclk[crtc->pipe] = min_cdclk; in intel_modeset_readout_hw_state()613 cdclk_state->min_voltage_level[crtc->pipe] = in intel_modeset_readout_hw_state()
900 const struct intel_cdclk_state *cdclk_state; in intel_bw_calc_min_cdclk() local945 cdclk_state = intel_atomic_get_cdclk_state(state); in intel_bw_calc_min_cdclk()946 if (IS_ERR(cdclk_state)) in intel_bw_calc_min_cdclk()947 return PTR_ERR(cdclk_state); in intel_bw_calc_min_cdclk()957 if (new_min_cdclk <= cdclk_state->bw_min_cdclk) in intel_bw_calc_min_cdclk()962 new_min_cdclk, cdclk_state->bw_min_cdclk); in intel_bw_calc_min_cdclk()
255 const struct intel_cdclk_state *cdclk_state; in intel_plane_calc_min_cdclk() local280 cdclk_state = intel_atomic_get_cdclk_state(state); in intel_plane_calc_min_cdclk()281 if (IS_ERR(cdclk_state)) in intel_plane_calc_min_cdclk()282 return PTR_ERR(cdclk_state); in intel_plane_calc_min_cdclk()293 cdclk_state->min_cdclk[crtc->pipe]) in intel_plane_calc_min_cdclk()301 cdclk_state->min_cdclk[crtc->pipe]); in intel_plane_calc_min_cdclk()
1013 struct intel_cdclk_state *cdclk_state; in glk_force_audio_cdclk_commit() local1021 cdclk_state = intel_atomic_get_cdclk_state(state); in glk_force_audio_cdclk_commit()1022 if (IS_ERR(cdclk_state)) in glk_force_audio_cdclk_commit()1023 return PTR_ERR(cdclk_state); in glk_force_audio_cdclk_commit()1025 cdclk_state->force_min_cdclk = enable ? 2 * 96000 : 0; in glk_force_audio_cdclk_commit()
1153 const struct intel_cdclk_state *cdclk_state; in intel_fbc_check_plane() local1155 cdclk_state = intel_atomic_get_cdclk_state(state); in intel_fbc_check_plane()1156 if (IS_ERR(cdclk_state)) in intel_fbc_check_plane()1157 return PTR_ERR(cdclk_state); in intel_fbc_check_plane()1159 if (crtc_state->pixel_rate >= cdclk_state->logical.cdclk * 95 / 100) { in intel_fbc_check_plane()
4721 const struct intel_cdclk_state *cdclk_state) in hsw_ips_linetime_wm() argument4731 cdclk_state->logical.cdclk); in hsw_ips_linetime_wm()4764 const struct intel_cdclk_state *cdclk_state; in hsw_compute_linetime_wm() local4774 cdclk_state = intel_atomic_get_cdclk_state(state); in hsw_compute_linetime_wm()4775 if (IS_ERR(cdclk_state)) in hsw_compute_linetime_wm()4776 return PTR_ERR(cdclk_state); in hsw_compute_linetime_wm()4779 cdclk_state); in hsw_compute_linetime_wm()8347 struct intel_cdclk_state *cdclk_state; in intel_modeset_init_hw() local8352 cdclk_state = to_intel_cdclk_state(i915->display.cdclk.obj.state); in intel_modeset_init_hw()8356 cdclk_state->logical = cdclk_state->actual = i915->display.cdclk.hw; in intel_modeset_init_hw()
Completed in 35 milliseconds