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Searched refs:cgu (Results 1 – 25 of 62) sorted by relevance

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/linux-6.3-rc2/drivers/clk/ingenic/
A Dcgu.c84 struct ingenic_cgu *cgu = ingenic_clk->cgu; in ingenic_pll_recalc_rate() local
205 struct ingenic_cgu *cgu = ingenic_clk->cgu; in ingenic_pll_set_rate() local
250 struct ingenic_cgu *cgu = ingenic_clk->cgu; in ingenic_pll_enable() local
284 struct ingenic_cgu *cgu = ingenic_clk->cgu; in ingenic_pll_disable() local
305 struct ingenic_cgu *cgu = ingenic_clk->cgu; in ingenic_pll_is_enabled() local
336 struct ingenic_cgu *cgu = ingenic_clk->cgu; in ingenic_clk_get_parent() local
362 struct ingenic_cgu *cgu = ingenic_clk->cgu; in ingenic_clk_set_parent() local
410 struct ingenic_cgu *cgu = ingenic_clk->cgu; in ingenic_clk_recalc_rate() local
528 struct ingenic_cgu *cgu = ingenic_clk->cgu; in ingenic_clk_set_rate() local
683 ingenic_clk->cgu = cgu; in ingenic_register_clock()
[all …]
A DMakefile2 obj-$(CONFIG_INGENIC_CGU_COMMON) += cgu.o pm.o
3 obj-$(CONFIG_INGENIC_CGU_JZ4740) += jz4740-cgu.o
4 obj-$(CONFIG_INGENIC_CGU_JZ4755) += jz4755-cgu.o
5 obj-$(CONFIG_INGENIC_CGU_JZ4725B) += jz4725b-cgu.o
6 obj-$(CONFIG_INGENIC_CGU_JZ4760) += jz4760-cgu.o
7 obj-$(CONFIG_INGENIC_CGU_JZ4770) += jz4770-cgu.o
8 obj-$(CONFIG_INGENIC_CGU_JZ4780) += jz4780-cgu.o
9 obj-$(CONFIG_INGENIC_CGU_X1000) += x1000-cgu.o
10 obj-$(CONFIG_INGENIC_CGU_X1830) += x1830-cgu.o
A Djz4780-cgu.c103 static struct ingenic_cgu *cgu; variable
173 spin_lock_irqsave(&cgu->lock, flags); in jz4780_otg_phy_set_rate()
180 spin_unlock_irqrestore(&cgu->lock, flags); in jz4780_otg_phy_set_rate()
226 struct ingenic_cgu *cgu = ingenic_clk->cgu; in jz4780_core1_enable() local
232 spin_lock_irqsave(&cgu->lock, flags); in jz4780_core1_enable()
234 lcr = readl(cgu->base + CGU_REG_LCR); in jz4780_core1_enable()
236 writel(lcr, cgu->base + CGU_REG_LCR); in jz4780_core1_enable()
242 spin_unlock_irqrestore(&cgu->lock, flags); in jz4780_core1_enable()
793 cgu = ingenic_cgu_new(jz4780_cgu_clocks, in jz4780_cgu_init()
795 if (!cgu) { in jz4780_cgu_init()
[all …]
A Dx1000-cgu.c62 static struct ingenic_cgu *cgu; variable
70 usbpcr1 = readl(cgu->base + CGU_REG_USBPCR1); in x1000_otg_phy_recalc_rate()
122 spin_lock_irqsave(&cgu->lock, flags); in x1000_otg_phy_set_rate()
124 usbpcr1 = readl(cgu->base + CGU_REG_USBPCR1); in x1000_otg_phy_set_rate()
127 writel(usbpcr1, cgu->base + CGU_REG_USBPCR1); in x1000_otg_phy_set_rate()
129 spin_unlock_irqrestore(&cgu->lock, flags); in x1000_otg_phy_set_rate()
201 writel(0, cgu->base + CGU_REG_I2SCDR1); in x1000_i2spll_set_rate_hook()
545 cgu = ingenic_cgu_new(x1000_cgu_clocks, in x1000_cgu_init()
547 if (!cgu) { in x1000_cgu_init()
552 retval = ingenic_cgu_register_clocks(cgu); in x1000_cgu_init()
[all …]
A Dx1830-cgu.c55 static struct ingenic_cgu *cgu; variable
59 void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR; in x1830_usb_phy_enable()
60 void __iomem *reg_usbpcr = cgu->base + CGU_REG_USBPCR; in x1830_usb_phy_enable()
69 void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR; in x1830_usb_phy_disable()
70 void __iomem *reg_usbpcr = cgu->base + CGU_REG_USBPCR; in x1830_usb_phy_disable()
78 void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR; in x1830_usb_phy_is_enabled()
79 void __iomem *reg_usbpcr = cgu->base + CGU_REG_USBPCR; in x1830_usb_phy_is_enabled()
453 cgu = ingenic_cgu_new(x1830_cgu_clocks, in x1830_cgu_init()
455 if (!cgu) { in x1830_cgu_init()
460 retval = ingenic_cgu_register_clocks(cgu); in x1830_cgu_init()
[all …]
A Djz4770-cgu.c49 static struct ingenic_cgu *cgu; variable
53 void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR; in jz4770_uhc_phy_enable()
54 void __iomem *reg_usbpcr1 = cgu->base + CGU_REG_USBPCR1; in jz4770_uhc_phy_enable()
63 void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR; in jz4770_uhc_phy_disable()
64 void __iomem *reg_usbpcr1 = cgu->base + CGU_REG_USBPCR1; in jz4770_uhc_phy_disable()
72 void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR; in jz4770_uhc_phy_is_enabled()
73 void __iomem *reg_usbpcr1 = cgu->base + CGU_REG_USBPCR1; in jz4770_uhc_phy_is_enabled()
448 cgu = ingenic_cgu_new(jz4770_cgu_clocks, in jz4770_cgu_init()
450 if (!cgu) { in jz4770_cgu_init()
455 retval = ingenic_cgu_register_clocks(cgu); in jz4770_cgu_init()
[all …]
A Djz4725b-cgu.c33 static struct ingenic_cgu *cgu; variable
260 cgu = ingenic_cgu_new(jz4725b_cgu_clocks, in jz4725b_cgu_init()
262 if (!cgu) { in jz4725b_cgu_init()
267 retval = ingenic_cgu_register_clocks(cgu); in jz4725b_cgu_init()
271 ingenic_cgu_register_syscore_ops(cgu); in jz4725b_cgu_init()
A Djz4740-cgu.c48 static struct ingenic_cgu *cgu; variable
258 cgu = ingenic_cgu_new(jz4740_cgu_clocks, in jz4740_cgu_init()
260 if (!cgu) { in jz4740_cgu_init()
265 retval = ingenic_cgu_register_clocks(cgu); in jz4740_cgu_init()
269 ingenic_cgu_register_syscore_ops(cgu); in jz4740_cgu_init()
A Djz4755-cgu.c30 static struct ingenic_cgu *cgu; variable
329 cgu = ingenic_cgu_new(jz4755_cgu_clocks, in jz4755_cgu_init()
331 if (!cgu) { in jz4755_cgu_init()
336 retval = ingenic_cgu_register_clocks(cgu); in jz4755_cgu_init()
340 ingenic_cgu_register_syscore_ops(cgu); in jz4755_cgu_init()
/linux-6.3-rc2/Documentation/devicetree/bindings/clock/
A Dingenic,cgu.yaml23 - ingenic,jz4740-cgu
24 - ingenic,jz4725b-cgu
25 - ingenic,jz4755-cgu
26 - ingenic,jz4760-cgu
27 - ingenic,jz4760b-cgu
28 - ingenic,jz4770-cgu
29 - ingenic,jz4780-cgu
30 - ingenic,x1000-cgu
31 - ingenic,x1830-cgu
60 - ingenic,x1000-cgu
[all …]
A Dlpc1850-ccu.txt47 clocks = <&cgu BASE_APB3_CLK>, <&cgu BASE_APB1_CLK>,
48 <&cgu BASE_SPIFI_CLK>, <&cgu BASE_CPU_CLK>,
49 <&cgu BASE_PERIPH_CLK>, <&cgu BASE_USB0_CLK>,
50 <&cgu BASE_USB1_CLK>, <&cgu BASE_SPI_CLK>;
61 clocks = <&cgu BASE_AUDIO_CLK>, <&cgu BASE_UART3_CLK>,
62 <&cgu BASE_UART2_CLK>, <&cgu BASE_UART1_CLK>,
63 <&cgu BASE_UART0_CLK>, <&cgu BASE_SSP1_CLK>,
64 <&cgu BASE_SSP0_CLK>, <&cgu BASE_SDIO_CLK>;
A Dintel,cgu-lgm.yaml4 $id: http://devicetree.org/schemas/clock/intel,cgu-lgm.yaml#
23 const: intel,cgu-lgm
40 cgu: clock-controller@e0200000 {
41 compatible = "intel,cgu-lgm";
/linux-6.3-rc2/arch/mips/boot/dts/ingenic/
A Djz4740.dtsi19 clocks = <&cgu JZ4740_CLK_CCLK>;
53 cgu: jz4740-cgu@10000000 { label
72 clocks = <&cgu JZ4740_CLK_RTC>,
73 <&cgu JZ4740_CLK_EXT>,
74 <&cgu JZ4740_CLK_PCLK>,
75 <&cgu JZ4740_CLK_TCU>;
114 clocks = <&cgu JZ4740_CLK_RTC>;
196 <&cgu JZ4740_CLK_I2S>,
197 <&cgu JZ4740_CLK_EXT>,
198 <&cgu JZ4740_CLK_PLL_HALF>;
[all …]
A Djz4770.dtsi19 clocks = <&cgu JZ4770_CLK_CCLK>;
53 cgu: jz4770-cgu@10000000 { label
84 clocks = <&cgu JZ4770_CLK_RTC>,
85 <&cgu JZ4770_CLK_EXT>,
86 <&cgu JZ4770_CLK_PCLK>;
241 clocks = <&cgu JZ4770_CLK_AIC>, <&cgu JZ4770_CLK_I2S>,
242 <&cgu JZ4770_CLK_EXT>, <&cgu JZ4770_CLK_PLL0>;
258 clocks = <&cgu JZ4770_CLK_AIC>;
392 <&cgu JZ4770_CLK_GPU>,
393 <&cgu JZ4770_CLK_GPU>;
[all …]
A Djz4780.dtsi20 clocks = <&cgu JZ4780_CLK_CPU>;
29 clocks = <&cgu JZ4780_CLK_CORE1>;
63 cgu: jz4780-cgu@10000000 { label
79 clocks = <&cgu JZ4780_CLK_OTG1>;
105 clocks = <&cgu JZ4780_CLK_RTCLK>,
106 <&cgu JZ4780_CLK_EXCLK>,
107 <&cgu JZ4780_CLK_PCLK>;
269 clocks = <&cgu JZ4780_CLK_SSI0>;
454 clocks = <&cgu JZ4780_CLK_AHB0>, <&cgu JZ4780_CLK_HDMI>;
467 clocks = <&cgu JZ4780_CLK_TVE>, <&cgu JZ4780_CLK_LCD0PIXCLK>;
[all …]
A Djz4725b.dtsi19 clocks = <&cgu JZ4725B_CLK_CCLK>;
53 cgu: clock-controller@10000000 { label
54 compatible = "ingenic,jz4725b-cgu";
72 clocks = <&cgu JZ4725B_CLK_RTC>,
73 <&cgu JZ4725B_CLK_EXT>,
74 <&cgu JZ4725B_CLK_PCLK>,
75 <&cgu JZ4725B_CLK_TCU>;
123 clocks = <&cgu JZ4725B_CLK_RTC>;
202 <&cgu JZ4725B_CLK_I2S>,
203 <&cgu JZ4725B_CLK_EXT>,
[all …]
A Dx1000.dtsi20 clocks = <&cgu X1000_CLK_CPU>;
54 cgu: x1000-cgu@10000000 { label
96 clocks = <&cgu X1000_CLK_OST>;
112 clocks = <&cgu X1000_CLK_RTCLK>,
113 <&cgu X1000_CLK_EXCLK>,
114 <&cgu X1000_CLK_PCLK>,
115 <&cgu X1000_CLK_TCU>;
152 clocks = <&cgu X1000_CLK_RTCLK>;
271 clocks = <&cgu X1000_CLK_SSI>;
385 clocks = <&cgu X1000_CLK_MAC>;
[all …]
A Dx1830.dtsi20 clocks = <&cgu X1830_CLK_CPU>;
54 cgu: x1830-cgu@10000000 { label
89 clocks = <&cgu X1830_CLK_OST>;
105 clocks = <&cgu X1830_CLK_RTCLK>,
106 <&cgu X1830_CLK_EXCLK>,
107 <&cgu X1830_CLK_PCLK>,
108 <&cgu X1830_CLK_TCU>;
147 clocks = <&cgu X1830_CLK_RTCLK>;
253 clocks = <&cgu X1830_CLK_SSI0>;
395 clocks = <&cgu X1830_CLK_MAC>;
[all …]
A Dgcw0.dts440 &cgu {
451 <&cgu JZ4770_CLK_PLL1>,
452 <&cgu JZ4770_CLK_GPU>,
453 <&cgu JZ4770_CLK_RTC>,
454 <&cgu JZ4770_CLK_UHC>,
460 <&cgu JZ4770_CLK_PLL0>,
461 <&cgu JZ4770_CLK_OSC32K>,
462 <&cgu JZ4770_CLK_PLL1>,
463 <&cgu JZ4770_CLK_PLL1>,
464 <&cgu JZ4770_CLK_PLL1>,
[all …]
/linux-6.3-rc2/arch/arm/boot/dts/
A Dlpc18xx.dtsi16 #include "dt-bindings/clock/lpc18xx-cgu.h"
232 cgu: clock-controller@40050000 { label
233 compatible = "nxp,lpc1850-cgu";
243 clocks = <&cgu BASE_APB3_CLK>, <&cgu BASE_APB1_CLK>,
244 <&cgu BASE_SPIFI_CLK>, <&cgu BASE_CPU_CLK>,
245 <&cgu BASE_PERIPH_CLK>, <&cgu BASE_USB0_CLK>,
246 <&cgu BASE_USB1_CLK>, <&cgu BASE_SPI_CLK>;
257 clocks = <&cgu BASE_AUDIO_CLK>, <&cgu BASE_UART3_CLK>,
258 <&cgu BASE_UART2_CLK>, <&cgu BASE_UART1_CLK>,
259 <&cgu BASE_UART0_CLK>, <&cgu BASE_SSP1_CLK>,
[all …]
/linux-6.3-rc2/Documentation/devicetree/bindings/mips/lantiq/
A Dlantiq,cgu.yaml4 $id: http://devicetree.org/schemas/mips/lantiq/lantiq,cgu.yaml#
16 - lantiq,cgu-xway
29 cgu@103000 {
30 compatible = "lantiq,cgu-xway";
/linux-6.3-rc2/Documentation/devicetree/bindings/display/
A Dingenic,lcd.yaml93 #include <dt-bindings/clock/ingenic,jz4740-cgu.h>
101 clocks = <&cgu JZ4740_CLK_LCD_PCLK>, <&cgu JZ4740_CLK_LCD>;
112 #include <dt-bindings/clock/ingenic,jz4725b-cgu.h>
120 clocks = <&cgu JZ4725B_CLK_LCD>;
/linux-6.3-rc2/Documentation/devicetree/bindings/rtc/
A Dingenic,rtc.yaml89 #include <dt-bindings/clock/ingenic,jz4740-cgu.h>
97 clocks = <&cgu JZ4740_CLK_RTC>;
102 #include <dt-bindings/clock/ingenic,jz4780-cgu.h>
110 clocks = <&cgu JZ4780_CLK_RTCLK>;
/linux-6.3-rc2/Documentation/devicetree/bindings/mmc/
A Dingenic,mmc.yaml65 #include <dt-bindings/clock/ingenic,jz4780-cgu.h>
74 clocks = <&cgu JZ4780_CLK_MSC0>;
85 #include <dt-bindings/clock/ingenic,jz4780-cgu.h>
99 clocks = <&cgu JZ4780_CLK_MSC1>;
/linux-6.3-rc2/drivers/clk/x86/
A DMakefile4 obj-$(CONFIG_CLK_LGM_CGU) += clk-cgu.o clk-cgu-pll.o clk-lgm.o

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