Home
last modified time | relevance | path

Searched refs:clk_base (Results 1 – 22 of 22) sorted by relevance

/linux-6.3-rc2/drivers/clk/tegra/
A Dclk-tegra210.c532 fence_udelay(1, clk_base); in tegra210_plle_hw_sequence_start()
537 fence_udelay(1, clk_base); in tegra210_plle_hw_sequence_start()
635 fence_udelay(1, clk_base); in tegra210_generic_mbist_war()
637 fence_udelay(1, clk_base); in tegra210_generic_mbist_war()
649 fence_udelay(1, clk_base); in tegra210_venc_mbist_war()
655 fence_udelay(1, clk_base); in tegra210_venc_mbist_war()
660 fence_udelay(1, clk_base); in tegra210_venc_mbist_war()
671 fence_udelay(1, clk_base); in tegra210_disp_mbist_war()
680 fence_udelay(1, clk_base); in tegra210_disp_mbist_war()
3335 clk_base, pmc, 0, in tegra210_pll_init()
[all …]
A Dclk-tegra-super-gen4.c109 clk_base + SCLK_BURST_POLICY, in tegra_sclk_init()
119 clk_base + SCLK_DIVIDER, 0, 8, in tegra_sclk_init()
132 clk_base + SCLK_BURST_POLICY, in tegra_sclk_init()
142 clk_base + SYSTEM_CLK_RATE, 4, 2, 0, in tegra_sclk_init()
146 clk_base + SYSTEM_CLK_RATE, in tegra_sclk_init()
157 clk_base + SYSTEM_CLK_RATE, 0, 2, 0, in tegra_sclk_init()
160 CLK_IS_CRITICAL, clk_base + SYSTEM_CLK_RATE, in tegra_sclk_init()
182 clk_base + CCLKG_BURST_POLICY, in tegra_super_clk_init()
189 clk_base + CCLKG_BURST_POLICY, in tegra_super_clk_init()
208 clk_base + CCLKLP_BURST_POLICY, in tegra_super_clk_init()
[all …]
A Dclk-tegra20.c133 static void __iomem *clk_base; variable
654 clk_base + PLLM_OUT, 1, 0, in tegra20_pll_init()
735 clk_base + AUDIO_SYNC_CLK, 4, in tegra20_audio_clk_init()
849 clk_base, data->offset); in tegra20_periph_clk_init()
882 reg = readl(clk_base + in tegra20_wait_cpu_in_reset()
945 readl(clk_base + PLLX_BASE); in tegra20_cpu_clock_suspend()
947 readl(clk_base + PLLX_MISC); in tegra20_cpu_clock_suspend()
976 clk_base + PLLX_MISC); in tegra20_cpu_clock_resume()
978 clk_base + PLLX_BASE); in tegra20_cpu_clock_resume()
1122 clk_base = of_iomap(np, 0); in tegra20_clock_init()
[all …]
A Dclk-tegra30.c151 static void __iomem *clk_base; variable
832 clk_base + PLLM_OUT, 1, 0, in tegra30_pll_init()
898 clk_base + SUPER_CCLKG_DIVIDER, 0, in tegra30_super_clk_init()
924 clk_base + CCLKG_BURST_POLICY, in tegra30_super_clk_init()
959 clk_base + CCLKLP_BURST_POLICY, in tegra30_super_clk_init()
1052 clk_base, data->offset); in tegra30_periph_clk_init()
1065 reg = readl(clk_base + in tegra30_wait_cpu_in_reset()
1109 cpu_rst_status = readl(clk_base + in tegra30_cpu_rail_off_ready()
1311 clk_base = of_iomap(np, 0); in tegra30_clock_init()
1312 if (!clk_base) { in tegra30_clock_init()
[all …]
A Dclk.h379 void __iomem *clk_base; member
405 void __iomem *clk_base, void __iomem *pmc,
410 void __iomem *clk_base, void __iomem *pmc,
421 void __iomem *clk_base, void __iomem *pmc,
427 void __iomem *clk_base, void __iomem *pmc,
433 void __iomem *clk_base, void __iomem *pmc,
446 void __iomem *clk_base, unsigned long flags,
452 void __iomem *clk_base, unsigned long flags,
474 void __iomem *clk_base, void __iomem *pmc,
480 void __iomem *clk_base, unsigned long flags,
[all …]
A Dclk-tegra114.c130 static void __iomem *clk_base; variable
914 clk_base + PLLC_OUT, 1, 0, in tegra114_pll_init()
998 clk_base + PLLRE_BASE, 16, 4, 0, in tegra114_pll_init()
1052 clk_base + CLK_SOURCE_EMC, in tegra114_periph_clk_init()
1095 readl(clk_base + CLK_SOURCE_CSITE); in tegra114_cpu_clock_suspend()
1107 clk_base + CLK_SOURCE_CSITE); in tegra114_cpu_clock_resume()
1110 clk_base + CCLKG_BURST_POLICY); in tegra114_cpu_clock_resume()
1307 clk_base = of_iomap(np, 0); in tegra114_clock_init()
1308 if (!clk_base) { in tegra114_clock_init()
1338 tegra114_fixed_clk_init(clk_base); in tegra114_clock_init()
[all …]
A Dclk-periph-gate.c20 readl_relaxed(gate->clk_base + (gate->regs->enb_reg))
22 writel_relaxed(val, gate->clk_base + (gate->regs->enb_set_reg))
24 writel_relaxed(val, gate->clk_base + (gate->regs->enb_clr_reg))
27 readl_relaxed(gate->clk_base + (gate->regs->rst_reg))
29 writel_relaxed(val, gate->clk_base + (gate->regs->rst_clr_reg))
59 writel_relaxed(0, gate->clk_base + LVL2_CLK_GATE_OVRE); in clk_periph_enable_locked()
60 writel_relaxed(BIT(22), gate->clk_base + LVL2_CLK_GATE_OVRE); in clk_periph_enable_locked()
62 writel_relaxed(0, gate->clk_base + LVL2_CLK_GATE_OVRE); in clk_periph_enable_locked()
137 const char *parent_name, u8 gate_flags, void __iomem *clk_base, in tegra_clk_register_periph_gate() argument
162 gate->clk_base = clk_base; in tegra_clk_register_periph_gate()
A Dclk-tegra-audio.c148 clk_base + data->offset, 0, 3, 0, in tegra_audio_sync_clk_init()
157 0, clk_base + data->offset, 4, in tegra_audio_sync_clk_init()
163 void __init tegra_audio_clk_init(void __iomem *clk_base, in tegra_audio_clk_init() argument
184 clk_base, pmc_base, 0, info->pll_params, in tegra_audio_clk_init()
194 clk_base + PLLA_OUT, 0, TEGRA_DIVIDER_ROUND_UP, in tegra_audio_clk_init()
197 clk_base + PLLA_OUT, 1, 0, CLK_IGNORE_UNUSED | in tegra_audio_clk_init()
215 tegra_audio_sync_clk_init(clk_base, tegra_clks, audio_clks, in tegra_audio_clk_init()
221 writel_relaxed(1, clk_base + dmic_clks[i].offset); in tegra_audio_clk_init()
223 tegra_audio_sync_clk_init(clk_base, tegra_clks, dmic_clks, in tegra_audio_clk_init()
238 data->name_2x, clk_base + AUDIO_SYNC_DOUBLER, in tegra_audio_clk_init()
[all …]
A Dclk-tegra124.c119 static void __iomem *clk_base; variable
1044 clk_base, 0, 48, in tegra124_periph_clk_init()
1049 clk_base, 0, 82, in tegra124_periph_clk_init()
1102 clk_base + PLLC_OUT, 1, 0, in tegra124_pll_init()
1136 clk_base + PLLM_OUT, 1, 0, in tegra124_pll_init()
1197 clk_base + PLLRE_BASE, 16, 4, 0, in tegra124_pll_init()
1255 readl(clk_base + CLK_SOURCE_CSITE); in tegra124_cpu_clock_suspend()
1267 clk_base + CLK_SOURCE_CSITE); in tegra124_cpu_clock_resume()
1270 clk_base + CCLKG_BURST_POLICY); in tegra124_cpu_clock_resume()
1461 clk_base = of_iomap(np, 0); in tegra124_132_clock_init_pre()
[all …]
A Dclk-tegra-fixed.c25 int __init tegra_osc_clk_init(void __iomem *clk_base, struct tegra_clk *clks, in tegra_osc_clk_init() argument
35 val = readl_relaxed(clk_base + OSC_CTRL); in tegra_osc_clk_init()
110 void tegra_clk_osc_resume(void __iomem *clk_base) in tegra_clk_osc_resume() argument
114 val = readl_relaxed(clk_base + OSC_CTRL) & ~OSC_CTRL_MASK; in tegra_clk_osc_resume()
116 writel_relaxed(val, clk_base + OSC_CTRL); in tegra_clk_osc_resume()
117 fence_udelay(2, clk_base); in tegra_clk_osc_resume()
A Dclk-periph.c164 void __iomem *clk_base, u32 offset, in _tegra_clk_register_periph() argument
192 periph->mux.reg = clk_base + offset; in _tegra_clk_register_periph()
193 periph->divider.reg = div ? (clk_base + offset) : NULL; in _tegra_clk_register_periph()
194 periph->gate.clk_base = clk_base; in _tegra_clk_register_periph()
211 struct tegra_clk_periph *periph, void __iomem *clk_base, in tegra_clk_register_periph() argument
215 periph, clk_base, offset, flags); in tegra_clk_register_periph()
220 struct tegra_clk_periph *periph, void __iomem *clk_base, in tegra_clk_register_periph_nodiv() argument
225 periph, clk_base, offset, CLK_SET_RATE_PARENT); in tegra_clk_register_periph_nodiv()
228 struct clk *tegra_clk_register_periph_data(void __iomem *clk_base, in tegra_clk_register_periph_data() argument
233 clk_base, init->offset, init->flags); in tegra_clk_register_periph_data()
A Dclk.c99 static void __iomem *clk_base; variable
115 clk_base + periph_regs[id / 32].rst_set_reg); in tegra_clk_rst_assert()
168 val = readl_relaxed(clk_base + CLK_OUT_ENB_Y); in tegra_clk_set_pllp_out_cpu()
174 writel_relaxed(val, clk_base + CLK_OUT_ENB_Y); in tegra_clk_set_pllp_out_cpu()
184 readl_relaxed(clk_base + periph_regs[i].enb_reg); in tegra_clk_periph_suspend()
188 readl_relaxed(clk_base + periph_regs[i].rst_reg); in tegra_clk_periph_suspend()
198 clk_base + periph_regs[i].enb_reg); in tegra_clk_periph_resume()
204 fence_udelay(5, clk_base); in tegra_clk_periph_resume()
208 clk_base + periph_regs[i].rst_reg); in tegra_clk_periph_resume()
210 fence_udelay(2, clk_base); in tegra_clk_periph_resume()
[all …]
A Dclk-pll.c302 lock_addr = pll->clk_base; in clk_pll_wait_for_lock()
1002 val = readl(pll->clk_base + PLLE_SS_CTRL); in clk_plle_enable()
1005 writel(val, pll->clk_base + PLLE_SS_CTRL); in clk_plle_enable()
1268 void __iomem *clk_base, in _setup_dynamic_ramp() argument
1864 fence_udelay(1, pll->clk_base); in _clk_plle_tegra_init_parent()
1879 pll->clk_base = clk_base; in _tegra_init_pll()
1921 void __iomem *clk_base, void __iomem *pmc, in tegra_clk_register_pll() argument
1952 void __iomem *clk_base, void __iomem *pmc, in tegra_clk_register_plle() argument
1977 void __iomem *clk_base, unsigned long flags, in tegra_clk_register_pllu() argument
2043 void __iomem *clk_base, void __iomem *pmc, in tegra_clk_register_pllxc() argument
[all …]
A Dclk-tegra-periph.c905 clk_base, data->flags, in gate_clk_init()
929 data->p.parent_name, clk_base + data->offset, in div_clk_init()
966 clk_base + data->offset, 0, data->div_flags, in init_pllp()
969 data->div_name, clk_base + data->offset, in init_pllp()
987 "pll_p_out_cpu", clk_base + PLLP_OUTB, 0, 0, 24, in init_pllp()
993 "pll_p_out4_div", clk_base + PLLP_OUTB, in init_pllp()
1006 clk_base + PLLP_MISC1, 29, 0, NULL); in init_pllp()
1015 CLK_IGNORE_UNUSED, clk_base + PLLP_MISC1, 28, 0, in init_pllp()
1027 periph_clk_init(clk_base, tegra_clks); in tegra_periph_clk_init()
1028 gate_clk_init(clk_base, tegra_clks); in tegra_periph_clk_init()
[all …]
A Dclk-sdmmc-mux.c235 void __iomem *clk_base, u32 offset, u32 clk_num, u8 div_flags, in tegra_clk_register_sdmmc_mux_div() argument
259 sdmmc_mux->reg = clk_base + offset; in tegra_clk_register_sdmmc_mux_div()
261 sdmmc_mux->gate.clk_base = clk_base; in tegra_clk_register_sdmmc_mux_div()
/linux-6.3-rc2/drivers/clk/
A Dclk-npcm7xx.c407 void __iomem *clk_base; in npcm7xx_clk_init() local
420 clk_base = ioremap(res.start, resource_size(&res)); in npcm7xx_clk_init()
421 if (!clk_base) in npcm7xx_clk_init()
438 hw = npcm7xx_clk_register_pll(clk_base + pll_data->reg, in npcm7xx_clk_init()
471 mux_data->flags, clk_base + NPCM7XX_CLKSEL, in npcm7xx_clk_init()
491 clk_base + div_data->reg, in npcm7xx_clk_init()
515 iounmap(clk_base); in npcm7xx_clk_init()
/linux-6.3-rc2/drivers/pinctrl/samsung/
A Dpinctrl-exynos-arm.c45 void __iomem *clk_base = (void __iomem *)drvdata->retention_ctrl->priv; in s5pv210_retention_disable() local
48 tmp = __raw_readl(clk_base + S5P_OTHERS); in s5pv210_retention_disable()
51 __raw_writel(tmp, clk_base + S5P_OTHERS); in s5pv210_retention_disable()
60 void __iomem *clk_base; in s5pv210_retention_init() local
73 clk_base = of_iomap(np, 0); in s5pv210_retention_init()
75 if (!clk_base) { in s5pv210_retention_init()
80 ctrl->priv = (void __force *)clk_base; in s5pv210_retention_init()
A Dpinctrl-exynos.c382 void __iomem *clk_base; in s5pv210_pinctrl_set_eint_wakeup_mask() local
391 clk_base = (void __iomem *) drvdata->retention_ctrl->priv; in s5pv210_pinctrl_set_eint_wakeup_mask()
394 clk_base + irq_chip->eint_wake_mask_reg); in s5pv210_pinctrl_set_eint_wakeup_mask()
/linux-6.3-rc2/drivers/cpufreq/
A Ds5pv210-cpufreq.c24 static void __iomem *clk_base; variable
27 #define S5P_CLKREG(x) (clk_base + (x))
624 clk_base = of_iomap(np, 0); in s5pv210_cpufreq_probe()
626 if (!clk_base) { in s5pv210_cpufreq_probe()
670 iounmap(clk_base); in s5pv210_cpufreq_probe()
A Darmada-37xx-cpufreq.c135 struct regmap *clk_base, u8 *divider) in armada37xx_cpufreq_dvfs_setup() argument
141 regmap_read(clk_base, ARMADA_37XX_CLK_TBG_SEL, &cpu_tbg_sel); in armada37xx_cpufreq_dvfs_setup()
/linux-6.3-rc2/drivers/clk/nxp/
A Dclk-lpc18xx-cgu.c634 static struct clk *clk_base[BASE_CLK_MAX]; variable
636 .clks = clk_base,
645 clk_base[i] = lpc18xx_register_base_clk(&lpc18xx_cgu_base_clks[i], in lpc18xx_cgu_register_base_clks()
647 if (IS_ERR(clk_base[i]) && PTR_ERR(clk_base[i]) != -ENOENT) in lpc18xx_cgu_register_base_clks()
/linux-6.3-rc2/drivers/mmc/host/
A Dsdhci-of-at91.c173 unsigned int clk_base, clk_mul; in sdhci_at91_set_clks_presets() local
187 clk_base = clk_base_rate / 1000000; in sdhci_at91_set_clks_presets()
191 caps0 |= FIELD_PREP(SDHCI_CLOCK_V3_BASE_MASK, clk_base); in sdhci_at91_set_clks_presets()

Completed in 68 milliseconds