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Searched refs:clk_div_mask (Results 1 – 11 of 11) sorted by relevance

/linux-6.3-rc2/drivers/clk/imx/
A Dclk-divider-gate.c33 val &= clk_div_mask(div->width); in clk_divider_gate_recalc_rate_ro()
55 val &= clk_div_mask(div->width); in clk_divider_gate_recalc_rate()
91 val &= ~(clk_div_mask(div->width) << div->shift); in clk_divider_gate_set_rate()
137 val &= clk_div_mask(div->width); in clk_divider_disable()
150 val &= clk_div_mask(div->width); in clk_divider_is_enabled()
210 val &= clk_div_mask(width); in imx_clk_hw_divider_gate()
A Dclk-composite-8m.c37 prediv_value &= clk_div_mask(divider->width); in imx8m_clk_composite_divider_recalc_rate()
44 div_value &= clk_div_mask(PCG_DIV_WIDTH); in imx8m_clk_composite_divider_recalc_rate()
110 val &= ~((clk_div_mask(divider->width) << divider->shift) | in imx8m_clk_composite_divider_set_rate()
111 (clk_div_mask(PCG_DIV_WIDTH) << PCG_DIV_SHIFT)); in imx8m_clk_composite_divider_set_rate()
A Dclk-composite-93.c123 val &= ~(clk_div_mask(divider->width) << divider->shift); in imx93_clk_composite_divider_set_rate()
/linux-6.3-rc2/drivers/clk/
A Dclk-divider.c48 unsigned int maxdiv = 0, mask = clk_div_mask(width); in _get_table_maxdiv()
72 return clk_div_mask(width); in _get_maxdiv()
74 return 1 << clk_div_mask(width); in _get_maxdiv()
77 return clk_div_mask(width) + 1; in _get_maxdiv()
99 return val ? val : clk_div_mask(width) + 1; in _get_div()
124 return (div == clk_div_mask(width) + 1) ? 0 : div; in _get_val()
156 val &= clk_div_mask(divider->width); in clk_divider_recalc_rate()
438 val &= clk_div_mask(divider->width); in clk_divider_round_rate()
459 val &= clk_div_mask(divider->width); in clk_divider_determine_rate()
483 return min_t(unsigned int, value, clk_div_mask(width)); in divider_get_val()
[all …]
A Dclk-milbeaut.c383 val &= clk_div_mask(divider->width); in m10v_clk_divider_recalc_rate()
399 val &= clk_div_mask(divider->width); in m10v_clk_divider_round_rate()
430 val &= ~(clk_div_mask(divider->width) << divider->shift); in m10v_clk_divider_set_rate()
A Dclk-bm1880.c602 val &= clk_div_mask(div->width); in bm1880_clk_div_recalc_rate()
622 val &= clk_div_mask(div->width); in bm1880_clk_div_round_rate()
654 val &= ~(clk_div_mask(div->width) << div_hw->div.shift); in bm1880_clk_div_set_rate()
/linux-6.3-rc2/drivers/clk/microchip/
A Dclk-mpfs.c105 mult &= clk_div_mask(MSSPLL_FBDIV_WIDTH); in mpfs_clk_msspll_recalc_rate()
107 ref_div &= clk_div_mask(MSSPLL_REFDIV_WIDTH); in mpfs_clk_msspll_recalc_rate()
109 postdiv &= clk_div_mask(MSSPLL_POSTDIV_WIDTH); in mpfs_clk_msspll_recalc_rate()
123 mult &= clk_div_mask(MSSPLL_FBDIV_WIDTH); in mpfs_clk_msspll_round_rate()
125 ref_div &= clk_div_mask(MSSPLL_REFDIV_WIDTH); in mpfs_clk_msspll_round_rate()
144 mult &= clk_div_mask(MSSPLL_FBDIV_WIDTH); in mpfs_clk_msspll_set_rate()
146 ref_div &= clk_div_mask(MSSPLL_REFDIV_WIDTH); in mpfs_clk_msspll_set_rate()
158 postdiv &= ~(clk_div_mask(MSSPLL_POSTDIV_WIDTH) << MSSPLL_POSTDIV_SHIFT); in mpfs_clk_msspll_set_rate()
A Dclk-mpfs-ccc.c81 mult &= clk_div_mask(MPFS_CCC_FBDIV_WIDTH); in mpfs_ccc_pll_recalc_rate()
83 ref_div &= clk_div_mask(MPFS_CCC_REFDIV_WIDTH); in mpfs_ccc_pll_recalc_rate()
/linux-6.3-rc2/drivers/clk/meson/
A Dclk-regmap.c73 val &= clk_div_mask(div->width); in clk_regmap_div_recalc_rate()
93 val &= clk_div_mask(div->width); in clk_regmap_div_determine_rate()
118 clk_div_mask(div->width) << div->shift, val); in clk_regmap_div_set_rate()
/linux-6.3-rc2/drivers/clk/stm32/
A Dclk-stm32-core.c215 val &= clk_div_mask(divider->width); in stm32_divider_get_rate()
243 val = clk_div_mask(divider->width) << (divider->shift + 16); in stm32_divider_set_rate()
246 val &= ~(clk_div_mask(divider->width) << divider->shift); in stm32_divider_set_rate()
367 val &= clk_div_mask(divider->width); in clk_stm32_divider_round_rate()
445 val &= clk_div_mask(divider->width); in clk_stm32_composite_round_rate()
/linux-6.3-rc2/include/linux/
A Dclk-provider.h670 #define clk_div_mask(width) ((1 << (width)) - 1) macro

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