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Searched refs:clkdm_offs (Results 1 – 9 of 9) sorted by relevance

/linux-6.3-rc2/arch/arm/mach-omap2/
A Dclockdomains33xx_data.c21 .clkdm_offs = AM33XX_CM_PER_L4LS_CLKSTCTRL_OFFSET,
29 .clkdm_offs = AM33XX_CM_PER_L3S_CLKSTCTRL_OFFSET,
37 .clkdm_offs = AM33XX_CM_PER_L4FW_CLKSTCTRL_OFFSET,
45 .clkdm_offs = AM33XX_CM_PER_L3_CLKSTCTRL_OFFSET,
53 .clkdm_offs = AM33XX_CM_PER_L4HS_CLKSTCTRL_OFFSET,
101 .clkdm_offs = AM33XX_CM_WKUP_CLKSTCTRL_OFFSET,
109 .clkdm_offs = AM33XX_CM_L3_AON_CLKSTCTRL_OFFSET,
125 .clkdm_offs = AM33XX_CM_MPU_CLKSTCTRL_OFFSET,
133 .clkdm_offs = AM33XX_CM_RTC_CLKSTCTRL_OFFSET,
141 .clkdm_offs = AM33XX_CM_GFX_L3_CLKSTCTRL_OFFSET,
[all …]
A Dclockdomains43xx_data.c20 .clkdm_offs = AM43XX_CM_CEFUSE_CEFUSE_CDOFFS,
29 .clkdm_offs = AM43XX_CM_MPU_MPU_CDOFFS,
38 .clkdm_offs = AM43XX_CM_PER_L4LS_CDOFFS,
56 .clkdm_offs = AM43XX_CM_RTC_RTC_CDOFFS,
65 .clkdm_offs = AM43XX_CM_PER_ICSS_CDOFFS,
92 .clkdm_offs = AM43XX_CM_PER_LCDC_CDOFFS,
101 .clkdm_offs = AM43XX_CM_PER_DSS_CDOFFS,
119 .clkdm_offs = AM43XX_CM_PER_EMIF_CDOFFS,
136 .clkdm_offs = AM43XX_CM_PER_L3_CDOFFS,
154 .clkdm_offs = AM43XX_CM_PER_CPSW_CDOFFS,
[all …]
A Dclockdomains81xx_data.c34 .clkdm_offs = TI81XX_CM_ALWON_L3_SLOW_CLKDM,
42 .clkdm_offs = TI81XX_CM_ALWON_L3_MED_CLKDM,
58 .clkdm_offs = TI81XX_CM_ETHERNET_CLKDM,
66 .clkdm_offs = TI81XX_CM_MMU_CLKDM,
74 .clkdm_offs = TI81XX_CM_MMUCFG_CLKDM,
100 .clkdm_offs = TI81XX_CM_ALWON_MPU_CLKDM,
108 .clkdm_offs = TI816X_CM_ACTIVE_GEM_CLKDM,
116 .clkdm_offs = TI816X_CM_IVAHD0_CLKDM,
124 .clkdm_offs = TI816X_CM_IVAHD1_CLKDM,
132 .clkdm_offs = TI816X_CM_IVAHD2_CLKDM,
[all …]
A Dclockdomains54xx_data.c169 .clkdm_offs = OMAP54XX_CM_CORE_CORE_L4SEC_CDOFFS,
181 .clkdm_offs = OMAP54XX_CM_CORE_IVA_IVA_CDOFFS,
233 .clkdm_offs = OMAP54XX_CM_CORE_CORE_IPU_CDOFFS,
245 .clkdm_offs = OMAP54XX_CM_CORE_CORE_L4CFG_CDOFFS,
265 .clkdm_offs = OMAP54XX_CM_CORE_DSS_DSS_CDOFFS,
289 .clkdm_offs = OMAP54XX_CM_CORE_CORE_C2C_CDOFFS,
310 .clkdm_offs = OMAP54XX_CM_CORE_GPU_GPU_CDOFFS,
382 .clkdm_offs = OMAP54XX_CM_CORE_CORE_DMA_CDOFFS,
401 .clkdm_offs = OMAP54XX_CM_CORE_CORE_EMIF_CDOFFS,
411 .clkdm_offs = OMAP54XX_PRM_EMU_CM_EMU_CDOFFS,
[all …]
A Dclockdomains7xx_data.c339 .clkdm_offs = DRA7XX_MPU_PRCM_CM_C0_CPU0_CDOFFS,
348 .clkdm_offs = DRA7XX_CM_CORE_IVA_IVA_CDOFFS,
381 .clkdm_offs = DRA7XX_CM_CORE_CORE_IPU2_CDOFFS,
490 .clkdm_offs = DRA7XX_CM_CORE_CORE_L4CFG_CDOFFS,
500 .clkdm_offs = DRA7XX_CM_CORE_CORE_DMA_CDOFFS,
532 .clkdm_offs = DRA7XX_CM_CORE_CORE_ATL_CDOFFS,
550 .clkdm_offs = DRA7XX_CM_CORE_DSS_DSS_CDOFFS,
562 .clkdm_offs = DRA7XX_CM_CORE_CORE_EMIF_CDOFFS,
572 .clkdm_offs = DRA7XX_PRM_EMU_CM_EMU_CDOFFS,
605 .clkdm_offs = DRA7XX_CM_CORE_CAM_CAM_CDOFFS,
[all …]
A Dclockdomains44xx_data.c167 .clkdm_offs = OMAP4430_CM2_CORE_L4CFG_CDOFFS,
177 .clkdm_offs = OMAP4430_CM1_TESLA_TESLA_CDOFFS,
189 .clkdm_offs = OMAP4430_CM2_GFX_GFX_CDOFFS,
235 .clkdm_offs = OMAP4430_CM1_ABE_ABE_CDOFFS,
265 .clkdm_offs = OMAP4430_CM2_CORE_D2D_CDOFFS,
325 .clkdm_offs = OMAP4430_CM1_MPU_MPU_CDOFFS,
336 .clkdm_offs = OMAP4430_CM2_CORE_L3_2_CDOFFS,
346 .clkdm_offs = OMAP4430_CM2_CORE_L3_1_CDOFFS,
356 .clkdm_offs = OMAP4430_CM2_CAM_CAM_CDOFFS,
367 .clkdm_offs = OMAP4430_CM2_DSS_DSS_CDOFFS,
[all …]
A Dcminst44xx.c355 clkdm1->cm_inst, clkdm1->clkdm_offs + in omap4_clkdm_add_wkup_sleep_dep()
365 clkdm1->cm_inst, clkdm1->clkdm_offs + in omap4_clkdm_del_wkup_sleep_dep()
375 clkdm1->clkdm_offs + in omap4_clkdm_read_wkup_sleep_dep()
397 clkdm->cm_inst, clkdm->clkdm_offs + in omap4_clkdm_clear_all_wkup_sleep_deps()
407 clkdm->clkdm_offs); in omap4_clkdm_sleep()
411 clkdm->clkdm_offs); in omap4_clkdm_sleep()
421 clkdm->cm_inst, clkdm->clkdm_offs); in omap4_clkdm_wakeup()
428 clkdm->cm_inst, clkdm->clkdm_offs); in omap4_clkdm_allow_idle()
438 clkdm->clkdm_offs); in omap4_clkdm_deny_idle()
468 clkdm->cm_inst, clkdm->clkdm_offs); in omap4_clkdm_clk_disable()
[all …]
A Dcm33xx.c299 am33xx_cm_clkdm_force_sleep(clkdm->cm_inst, clkdm->clkdm_offs); in am33xx_clkdm_sleep()
305 am33xx_cm_clkdm_force_wakeup(clkdm->cm_inst, clkdm->clkdm_offs); in am33xx_clkdm_wakeup()
311 am33xx_cm_clkdm_enable_hwsup(clkdm->cm_inst, clkdm->clkdm_offs); in am33xx_clkdm_allow_idle()
316 am33xx_cm_clkdm_disable_hwsup(clkdm->cm_inst, clkdm->clkdm_offs); in am33xx_clkdm_deny_idle()
331 hwsup = am33xx_cm_is_clkdm_in_hwsup(clkdm->cm_inst, clkdm->clkdm_offs); in am33xx_clkdm_clk_disable()
353 clkdm->clkdm_offs, in am33xx_clkdm_save_context()
A Dclockdomain.h135 const u16 clkdm_offs; member

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