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/linux-6.3-rc2/arch/arm/boot/dts/
A Dam43xx-clocks.dtsi9 #clock-cells = <0>;
18 #clock-cells = <0>;
40 clock-mult = <1>;
41 clock-div = <1>;
49 clock-mult = <1>;
50 clock-div = <1>;
59 clock-div = <1>;
68 clock-div = <1>;
77 clock-div = <1>;
86 clock-div = <1>;
[all …]
A Dam33xx-clocks.dtsi9 #clock-cells = <0>;
22 clock-mult = <1>;
23 clock-div = <1>;
31 clock-mult = <1>;
32 clock-div = <1>;
41 clock-div = <1>;
50 clock-div = <1>;
59 clock-div = <1>;
107 clock@664 {
565 clock@52c {
[all …]
A Domap3xxx-clocks.dtsi9 #clock-cells = <0>;
82 clock@68 {
119 clock@4 {
258 clock@1140 {
428 clock@d40 {
470 clock@e40 {
602 clock@d70 {
665 clock@a40 {
708 clock@c40 {
733 clock@a00 {
[all …]
A Ddra7xx-clocks.dtsi9 #clock-cells = <0>;
16 #clock-cells = <0>;
23 #clock-cells = <0>;
30 #clock-cells = <0>;
37 #clock-cells = <0>;
44 #clock-cells = <0>;
51 #clock-cells = <0>;
58 #clock-cells = <0>;
65 #clock-cells = <0>;
125 clock-mult = <1>;
[all …]
A Domap54xx-clocks.dtsi9 #clock-cells = <0>;
16 #clock-cells = <0>;
25 #clock-cells = <0>;
32 #clock-cells = <0>;
39 #clock-cells = <0>;
48 #clock-cells = <0>;
55 #clock-cells = <0>;
147 clock-mult = <1>;
148 clock-div = <8>;
230 clock-div = <1>;
[all …]
A Domap44xx-clocks.dtsi9 #clock-cells = <0>;
16 #clock-cells = <0>;
23 #clock-cells = <0>;
32 #clock-cells = <0>;
39 #clock-cells = <0>;
46 #clock-cells = <0>;
53 #clock-cells = <0>;
62 #clock-cells = <0>;
69 #clock-cells = <0>;
186 clock-div = <8>;
[all …]
A Domap24xx-clocks.dtsi9 #clock-cells = <0>;
17 #clock-cells = <0>;
23 #clock-cells = <0>;
31 #clock-cells = <0>;
39 #clock-cells = <0>;
45 #clock-cells = <0>;
86 clock-mult = <2>;
87 clock-div = <1>;
161 clock-div = <1>;
173 clock-div = <2>;
[all …]
A Dkeystone-clocks.dtsi14 #clock-cells = <0>;
24 #clock-cells = <0>;
27 clock-div = <1>;
28 clock-mult = <1>;
36 clock-div = <1>;
37 clock-mult = <1>;
65 clock-div = <2>;
74 clock-div = <3>;
83 clock-div = <3>;
92 clock-div = <4>;
[all …]
A Domap36xx-omap3430es2plus-clocks.dtsi8 clock@a00 {
11 #clock-cells = <2>;
15 #clock-cells = <0>;
23 clock@a40 {
49 clock-mult = <1>;
50 clock-div = <2>;
53 clock@a10 {
81 clock-div = <1>;
84 clock@c00 {
171 clock@c40 {
[all …]
A Domap34xx-omap36xx-clocks.dtsi9 #clock-cells = <0>;
12 clock-mult = <1>;
13 clock-div = <1>;
16 clock@a14 {
19 #clock-cells = <2>;
64 clock@f00 {
101 clock-div = <1>;
104 clock@a10 {
159 clock@c00 {
227 clock@a00 {
[all …]
A Ddm814x-clocks.dtsi10 #clock-cells = <1>;
22 #clock-cells = <1>;
33 #clock-cells = <1>;
44 #clock-cells = <1>;
55 #clock-cells = <1>;
66 #clock-cells = <1>;
77 #clock-cells = <1>;
88 #clock-cells = <1>;
99 #clock-cells = <1>;
254 clock-mult = <1>;
[all …]
A Dste-nomadik-stn8815.dtsi213 clock-div = <8>;
301 clock-id = <0>;
307 clock-id = <1>;
313 clock-id = <2>;
319 clock-id = <3>;
325 clock-id = <4>;
331 clock-id = <5>;
337 clock-id = <6>;
343 clock-id = <7>;
349 clock-id = <8>;
[all …]
A Domap36xx-am35xx-omap3430es2plus-clocks.dtsi9 #clock-cells = <0>;
12 clock-mult = <1>;
13 clock-div = <3>;
17 #clock-cells = <0>;
20 clock-mult = <1>;
21 clock-div = <5>;
56 clock-div = <3>;
137 clock@a18 {
152 clock@a10 {
167 clock@a00 {
[all …]
A Domap3430es1-clocks.dtsi9 #clock-cells = <0>;
17 #clock-cells = <0>;
26 #clock-cells = <0>;
29 clock-mult = <1>;
30 clock-div = <1>;
34 #clock-cells = <0>;
49 clock@a00 {
80 clock@a40 {
117 clock-div = <2>;
120 clock@a10 {
[all …]
A Dkeystone-k2hk-clocks.dtsi10 #clock-cells = <0>;
19 #clock-cells = <0>;
27 #clock-cells = <0>;
36 #clock-cells = <0>;
45 #clock-cells = <0>;
54 #clock-cells = <0>;
64 #clock-cells = <0>;
74 #clock-cells = <0>;
84 #clock-cells = <0>;
94 #clock-cells = <0>;
[all …]
A Ddm816x-clocks.dtsi5 #clock-cells = <1>;
21 #clock-cells = <1>;
33 #clock-cells = <1>;
44 #clock-cells = <1>;
59 #clock-cells = <0>;
65 #clock-cells = <0>;
71 #clock-cells = <0>;
77 #clock-cells = <0>;
86 #clock-cells = <0>;
94 #clock-cells = <0>;
[all …]
A Dexynos5420.dtsi288 clock: clock-controller@10010000 { label
321 clocks = <&clock CLK_MMC0>, <&clock CLK_SCLK_MMC0>;
333 clocks = <&clock CLK_MMC1>, <&clock CLK_SCLK_MMC1>;
345 clocks = <&clock CLK_MMC2>, <&clock CLK_SCLK_MMC2>;
800 clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
968 clocks = <&clock CLK_TMU>, <&clock CLK_TMU>;
977 clocks = <&clock CLK_TMU>, <&clock CLK_TMU_GPU>;
986 clocks = <&clock CLK_TMU_GPU>, <&clock CLK_TMU>;
997 clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>;
1007 clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>;
[all …]
A Dexynos5410.dtsi76 clock: clock-controller@10010000 { label
132 clocks = <&clock CLK_MMC0>, <&clock CLK_SCLK_MMC0>;
144 clocks = <&clock CLK_MMC1>, <&clock CLK_SCLK_MMC1>;
156 clocks = <&clock CLK_MMC2>, <&clock CLK_SCLK_MMC2>;
340 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
347 clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
354 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
361 clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
394 clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBPHY300>;
411 clocks = <&clock CLK_USBD301>, <&clock CLK_SCLK_USBPHY301>;
[all …]
A Dkeystone-k2l-clocks.dtsi10 #clock-cells = <0>;
19 #clock-cells = <0>;
27 #clock-cells = <0>;
36 #clock-cells = <0>;
45 #clock-cells = <0>;
55 #clock-cells = <0>;
65 #clock-cells = <0>;
75 #clock-cells = <0>;
85 #clock-cells = <0>;
95 #clock-cells = <0>;
[all …]
/linux-6.3-rc2/Documentation/devicetree/bindings/clock/
A Dsocionext,uniphier-clock.yaml4 $id: http://devicetree.org/schemas/clock/socionext,uniphier-clock.yaml#
7 title: UniPhier clock controller
15 - description: System clock
17 - socionext,uniphier-ld4-clock
27 - description: Media I/O (MIO) clock, SD clock
38 - description: Peripheral clock
49 - description: SoC-glue clock
53 "#clock-cells":
60 - "#clock-cells"
64 clock-controller {
[all …]
A Dlpc1850-cgu.txt10 clock sources, controls the clock generation, and routes the outputs
11 of the clock generators through the clock source bus to the output
19 Documentation/devicetree/bindings/clock/clock-bindings.txt
27 - #clock-cells:
34 - clock-indices:
37 - clock-output-names:
54 7 BASE_PHY_RX_CLK Base clock for Ethernet PHY Receive clock
55 8 BASE_PHY_TX_CLK Base clock for Ethernet PHY Transmit clock
70 26 BASE_CGU_OUT0_CLK Base clock for CGU_OUT0 clock output
71 27 BASE_CGU_OUT1_CLK Base clock for CGU_OUT1 clock output
[all …]
A Dmvebu-core-clock.txt5 specify the desired clock by having the clock ID in its "clocks" phandle cell.
9 1 = cpuclk (CPU clock)
12 4 = dramclk (DDR clock)
16 1 = cpuclk (CPU clock)
18 3 = ddrclk (DDR clock)
43 2 = l2clk (L2 Cache clock derived from CPU0 clock)
44 3 = ddrclk (DDR controller clock derived from CPU0 clock)
49 2 = ddrclk (DDR controller clock derived from CPU0 clock)
68 - #clock-cells : from common clock binding; shall be set to 1
71 - clock-output-names : from common clock binding; allows overwrite default clock
[all …]
A Dsamsung,exynos5260-clock.yaml4 $id: http://devicetree.org/schemas/clock/samsung,exynos5260-clock.yaml#
68 clock-names:
72 "#clock-cells":
80 - "#clock-cells"
94 clock-names:
101 - clock-names
114 clock-names:
143 clock-names:
161 clock-names:
179 clock-names:
[all …]
A Dtesla,fsd-clock.yaml4 $id: http://devicetree.org/schemas/clock/tesla,fsd-clock.yaml#
14 FSD clock controller consist of several clock management unit
16 The root clock comes from external OSC clock (24 MHz).
36 clock-names:
40 "#clock-cells":
57 clock-names:
74 clock-names:
96 clock-names:
118 clock-names:
173 - "#clock-cells"
[all …]
/linux-6.3-rc2/Documentation/devicetree/bindings/clock/ti/
A Dgate.txt5 This binding uses the common clock binding[1]. This clock is
12 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
13 [2] Documentation/devicetree/bindings/clock/gpio-gate-clock.yaml
18 "ti,gate-clock" - basic gate clock
19 "ti,wait-gate-clock" - gate clock which waits until clock is active before
21 "ti,dss-gate-clock" - gate clock with DSS specific hardware handling
29 clock
33 - #clock-cells : from common clock binding; shall be set to 0
39 - clock-output-names : from common clock binding.
43 gates the clock and clearing the bit ungates the clock.
[all …]

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