Home
last modified time | relevance | path

Searched refs:control_reg (Results 1 – 25 of 31) sorted by relevance

12

/linux-6.3-rc2/sound/pci/echoaudio/
A Dechoaudio_3g.c171 return control_reg; in set_spdif_bits()
179 u32 control_reg; in set_professional_spdif() local
183 control_reg = set_spdif_bits(chip, control_reg, chip->sample_rate); in set_professional_spdif()
304 control_reg |= clock; in set_sample_rate()
305 control_reg = set_spdif_bits(chip, control_reg, rate); in set_sample_rate()
331 u32 control_reg, clocks_from_dsp; in set_input_clock() local
346 control_reg |= E3G_SPDIF_CLOCK; in set_input_clock()
355 control_reg |= E3G_ADAT_CLOCK; in set_input_clock()
359 control_reg |= E3G_WORD_CLOCK; in set_input_clock()
379 u32 control_reg; in dsp_set_digital_mode() local
[all …]
A Dgina24_dsp.c126 u32 control_reg; in load_asic() local
166 u32 control_reg, clock; in set_sample_rate() local
200 if (control_reg & GML_SPDIF_PRO_MODE) in set_sample_rate()
225 control_reg |= clock; in set_sample_rate()
238 u32 control_reg, clocks_from_dsp; in set_input_clock() local
253 control_reg |= GML_SPDIF_CLOCK; in set_input_clock()
262 control_reg |= GML_ADAT_CLOCK; in set_input_clock()
266 control_reg |= GML_ESYNC_CLOCK; in set_input_clock()
286 u32 control_reg; in dsp_set_digital_mode() local
327 control_reg |= GML_SPDIF_CDROM_MODE; in dsp_set_digital_mode()
[all …]
A Dmona_dsp.c119 u32 control_reg; in load_asic() local
200 u32 control_reg, clock; in set_sample_rate() local
247 control_reg &= GML_CLOCK_CLEAR_MASK; in set_sample_rate()
263 if (control_reg & GML_SPDIF_PRO_MODE) in set_sample_rate()
288 control_reg |= clock; in set_sample_rate()
302 u32 control_reg, clocks_from_dsp; in set_input_clock() local
323 control_reg |= GML_SPDIF_CLOCK; in set_input_clock()
336 control_reg |= GML_WORD_CLOCK; in set_input_clock()
346 control_reg |= GML_ADAT_CLOCK; in set_input_clock()
363 u32 control_reg; in dsp_set_digital_mode() local
[all …]
A Dlayla24_dsp.c162 u32 control_reg, clock, base_rate; in set_sample_rate() local
197 if (control_reg & GML_SPDIF_PRO_MODE) in set_sample_rate()
222 control_reg |= GML_DOUBLE_SPEED_MODE; in set_sample_rate()
240 control_reg |= clock; in set_sample_rate()
254 u32 control_reg, clocks_from_dsp; in set_input_clock() local
269 control_reg |= GML_SPDIF_CLOCK; in set_input_clock()
271 control_reg &= ~GML_DOUBLE_SPEED_MODE; in set_input_clock()
274 control_reg |= GML_WORD_CLOCK; in set_input_clock()
283 control_reg |= GML_ADAT_CLOCK; in set_input_clock()
335 u32 control_reg; in dsp_set_digital_mode() local
[all …]
A Dechoaudio_gml.c158 u32 control_reg; in set_professional_spdif() local
162 control_reg = le32_to_cpu(chip->comm_page->control_register); in set_professional_spdif()
163 control_reg &= GML_SPDIF_FORMAT_CLEAR_MASK; in set_professional_spdif()
166 control_reg |= GML_SPDIF_TWO_CHANNEL | GML_SPDIF_24_BIT | in set_professional_spdif()
170 control_reg |= GML_SPDIF_PRO_MODE; in set_professional_spdif()
174 control_reg |= GML_SPDIF_SAMPLE_RATE0 | in set_professional_spdif()
178 control_reg |= GML_SPDIF_SAMPLE_RATE0; in set_professional_spdif()
181 control_reg |= GML_SPDIF_SAMPLE_RATE1; in set_professional_spdif()
188 control_reg |= GML_SPDIF_SAMPLE_RATE0 | in set_professional_spdif()
192 control_reg |= GML_SPDIF_SAMPLE_RATE1; in set_professional_spdif()
[all …]
A Dindigo_dsp.c94 u32 control_reg; in set_sample_rate() local
98 control_reg = MIA_96000; in set_sample_rate()
101 control_reg = MIA_88200; in set_sample_rate()
104 control_reg = MIA_48000; in set_sample_rate()
107 control_reg = MIA_44100; in set_sample_rate()
110 control_reg = MIA_32000; in set_sample_rate()
119 if (control_reg != le32_to_cpu(chip->comm_page->control_register)) { in set_sample_rate()
124 chip->comm_page->control_register = cpu_to_le32(control_reg); in set_sample_rate()
A Dindigodj_dsp.c94 u32 control_reg; in set_sample_rate() local
98 control_reg = MIA_96000; in set_sample_rate()
101 control_reg = MIA_88200; in set_sample_rate()
104 control_reg = MIA_48000; in set_sample_rate()
107 control_reg = MIA_44100; in set_sample_rate()
110 control_reg = MIA_32000; in set_sample_rate()
119 if (control_reg != le32_to_cpu(chip->comm_page->control_register)) { in set_sample_rate()
124 chip->comm_page->control_register = cpu_to_le32(control_reg); in set_sample_rate()
A Dmia_dsp.c111 u32 control_reg; in set_sample_rate() local
115 control_reg = MIA_96000; in set_sample_rate()
118 control_reg = MIA_88200; in set_sample_rate()
121 control_reg = MIA_48000; in set_sample_rate()
124 control_reg = MIA_44100; in set_sample_rate()
127 control_reg = MIA_32000; in set_sample_rate()
137 control_reg |= MIA_SPDIF; in set_sample_rate()
140 if (control_reg != le32_to_cpu(chip->comm_page->control_register)) { in set_sample_rate()
145 chip->comm_page->control_register = cpu_to_le32(control_reg); in set_sample_rate()
A Dindigo_express_dsp.c31 u32 clock, control_reg, old_control_reg; in set_sample_rate() local
37 control_reg = old_control_reg & ~INDIGO_EXPRESS_CLOCK_MASK; in set_sample_rate()
62 control_reg |= clock; in set_sample_rate()
63 if (control_reg != old_control_reg) { in set_sample_rate()
66 chip->comm_page->control_register = cpu_to_le32(control_reg); in set_sample_rate()
A Decho3g_dsp.c121 u32 control_reg = le32_to_cpu(chip->comm_page->control_register); in set_phantom_power() local
124 control_reg |= E3G_PHANTOM_POWER; in set_phantom_power()
126 control_reg &= ~E3G_PHANTOM_POWER; in set_phantom_power()
129 return write_control_reg(chip, control_reg, in set_phantom_power()
/linux-6.3-rc2/drivers/scsi/pcmcia/
A Dnsp_message.c15 unsigned char data_reg, control_reg; in nsp_message_in() local
33 control_reg = nsp_index_read(base, SCSIBUSCTRL); in nsp_message_in()
34 control_reg |= SCSI_ACK; in nsp_message_in()
35 nsp_index_write(base, SCSIBUSCTRL, control_reg); in nsp_message_in()
41 control_reg = nsp_index_read(base, SCSIBUSCTRL); in nsp_message_in()
42 control_reg &= ~SCSI_ACK; in nsp_message_in()
43 nsp_index_write(base, SCSIBUSCTRL, control_reg); in nsp_message_in()
/linux-6.3-rc2/drivers/clk/
A Dclk-palmas.c27 unsigned int control_reg; member
59 cinfo->clk_desc->control_reg, in palmas_clks_prepare()
64 cinfo->clk_desc->control_reg, ret); in palmas_clks_prepare()
84 cinfo->clk_desc->control_reg, in palmas_clks_unprepare()
88 cinfo->clk_desc->control_reg, ret); in palmas_clks_unprepare()
101 cinfo->clk_desc->control_reg, &val); in palmas_clks_is_prepared()
104 cinfo->clk_desc->control_reg, ret); in palmas_clks_is_prepared()
130 .control_reg = PALMAS_CLK32KG_CTRL,
146 .control_reg = PALMAS_CLK32KGAUDIO_CTRL,
203 cinfo->clk_desc->control_reg, in palmas_clks_init_configure()
[all …]
/linux-6.3-rc2/drivers/clk/ti/
A Dapll.c55 v = ti_clk_ll_ops->clk_readl(&ad->control_reg); in dra7_apll_enable()
58 ti_clk_ll_ops->clk_writel(v, &ad->control_reg); in dra7_apll_enable()
94 v = ti_clk_ll_ops->clk_readl(&ad->control_reg); in dra7_apll_disable()
97 ti_clk_ll_ops->clk_writel(v, &ad->control_reg); in dra7_apll_disable()
108 v = ti_clk_ll_ops->clk_readl(&ad->control_reg); in dra7_apll_is_enabled()
241 v = ti_clk_ll_ops->clk_readl(&ad->control_reg); in omap2_apll_is_enabled()
267 v = ti_clk_ll_ops->clk_readl(&ad->control_reg); in omap2_apll_enable()
270 ti_clk_ll_ops->clk_writel(v, &ad->control_reg); in omap2_apll_enable()
297 v = ti_clk_ll_ops->clk_readl(&ad->control_reg); in omap2_apll_disable()
300 ti_clk_ll_ops->clk_writel(v, &ad->control_reg); in omap2_apll_disable()
[all …]
A Ddpll3xxx.c54 v = ti_clk_ll_ops->clk_readl(&dd->control_reg); in _omap3_dpll_write_clken()
57 ti_clk_ll_ops->clk_writel(v, &dd->control_reg); in _omap3_dpll_write_clken()
308 ctrl = ti_clk_ll_ops->clk_readl(&dd->control_reg); in omap3_noncore_dpll_ssc_program()
373 ti_clk_ll_ops->clk_writel(ctrl, &dd->control_reg); in omap3_noncore_dpll_ssc_program()
399 v = ti_clk_ll_ops->clk_readl(&dd->control_reg); in omap3_noncore_dpll_program()
402 ti_clk_ll_ops->clk_writel(v, &dd->control_reg); in omap3_noncore_dpll_program()
456 v = ti_clk_ll_ops->clk_readl(&dd->control_reg); in omap3_noncore_dpll_program()
472 ti_clk_ll_ops->clk_writel(v, &dd->control_reg); in omap3_noncore_dpll_program()
884 v = ti_clk_ll_ops->clk_readl(&dd->control_reg); in omap3_core_dpll_save_context()
945 v = ti_clk_ll_ops->clk_readl(&dd->control_reg); in omap3_noncore_dpll_save_context()
[all …]
A Dclkt_dpll.c213 v = ti_clk_ll_ops->clk_readl(&dd->control_reg); in omap2_init_dpll_parent()
249 v = ti_clk_ll_ops->clk_readl(&dd->control_reg); in omap2_get_dpll_rate()
/linux-6.3-rc2/drivers/watchdog/
A Dts72xx_wdt.c45 void __iomem *control_reg; member
56 writeb(priv->regval, priv->control_reg); in ts72xx_wdt_start()
66 writeb(TS72XX_WDT_CTRL_DISABLE, priv->control_reg); in ts72xx_wdt_stop()
134 priv->control_reg = devm_platform_ioremap_resource(pdev, 0); in ts72xx_wdt_probe()
135 if (IS_ERR(priv->control_reg)) in ts72xx_wdt_probe()
136 return PTR_ERR(priv->control_reg); in ts72xx_wdt_probe()
/linux-6.3-rc2/drivers/tty/serial/
A Dpmac_zilog.h54 volatile u8 __iomem *control_reg; member
78 writeb(reg, port->control_reg); in read_zsreg()
79 return readb(port->control_reg); in read_zsreg()
85 writeb(reg, port->control_reg); in write_zsreg()
86 writeb(value, port->control_reg); in write_zsreg()
101 (void)readb(port->control_reg); in zssync()
/linux-6.3-rc2/arch/mips/cavium-octeon/executive/
A Dcvmx-helper-sgmii.c139 union cvmx_pcsx_mrx_control_reg control_reg; in __cvmx_helper_sgmii_hardware_init_link() local
149 control_reg.u64 = in __cvmx_helper_sgmii_hardware_init_link()
152 control_reg.s.reset = 1; in __cvmx_helper_sgmii_hardware_init_link()
154 control_reg.u64); in __cvmx_helper_sgmii_hardware_init_link()
169 control_reg.s.rst_an = 1; in __cvmx_helper_sgmii_hardware_init_link()
170 control_reg.s.an_en = 1; in __cvmx_helper_sgmii_hardware_init_link()
171 control_reg.s.pwr_dn = 0; in __cvmx_helper_sgmii_hardware_init_link()
173 control_reg.u64); in __cvmx_helper_sgmii_hardware_init_link()
/linux-6.3-rc2/drivers/power/supply/
A Dds2780_battery.c357 u8 *control_reg) in ds2780_get_control_register() argument
363 u8 control_reg) in ds2780_set_control_register() argument
367 ret = ds2780_write(dev_info, &control_reg, in ds2780_set_control_register()
448 u8 control_reg; in ds2780_get_pmod_enabled() local
453 ret = ds2780_get_control_register(dev_info, &control_reg); in ds2780_get_pmod_enabled()
458 !!(control_reg & DS2780_CONTROL_REG_PMOD)); in ds2780_get_pmod_enabled()
467 u8 control_reg, new_setting; in ds2780_set_pmod_enabled() local
472 ret = ds2780_get_control_register(dev_info, &control_reg); in ds2780_set_pmod_enabled()
486 control_reg |= DS2780_CONTROL_REG_PMOD; in ds2780_set_pmod_enabled()
488 control_reg &= ~DS2780_CONTROL_REG_PMOD; in ds2780_set_pmod_enabled()
[all …]
A Dds2781_battery.c359 u8 *control_reg) in ds2781_get_control_register() argument
365 u8 control_reg) in ds2781_set_control_register() argument
369 ret = ds2781_write(dev_info, &control_reg, in ds2781_set_control_register()
450 u8 control_reg; in ds2781_get_pmod_enabled() local
455 ret = ds2781_get_control_register(dev_info, &control_reg); in ds2781_get_pmod_enabled()
460 !!(control_reg & DS2781_CONTROL_PMOD)); in ds2781_get_pmod_enabled()
469 u8 control_reg, new_setting; in ds2781_set_pmod_enabled() local
474 ret = ds2781_get_control_register(dev_info, &control_reg); in ds2781_set_pmod_enabled()
488 control_reg |= DS2781_CONTROL_PMOD; in ds2781_set_pmod_enabled()
490 control_reg &= ~DS2781_CONTROL_PMOD; in ds2781_set_pmod_enabled()
[all …]
/linux-6.3-rc2/drivers/regulator/
A Das3722-regulator.c55 u32 control_reg; member
85 .control_reg = AS3722_SD0_CONTROL_REG,
97 .control_reg = AS3722_SD1_CONTROL_REG,
110 .control_reg = AS3722_SD23_CONTROL_REG,
124 .control_reg = AS3722_SD23_CONTROL_REG,
138 .control_reg = AS3722_SD4_CONTROL_REG,
152 .control_reg = AS3722_SD5_CONTROL_REG,
165 .control_reg = AS3722_SD6_CONTROL_REG,
427 if (!as3722_reg_lookup[id].control_reg) in as3722_sd_get_mode()
433 as3722_reg_lookup[id].control_reg, ret); in as3722_sd_get_mode()
[all …]
A Danatop-regulator.c166 u32 control_reg; in anatop_regulator_probe() local
203 ret = of_property_read_u32(np, "anatop-reg-offset", &control_reg); in anatop_regulator_probe()
247 rdesc->vsel_reg = control_reg; in anatop_regulator_probe()
258 if (control_reg && sreg->delay_bit_width) { in anatop_regulator_probe()
300 rdesc->enable_reg = control_reg; in anatop_regulator_probe()
A Dti-abb-regulator.c97 void __iomem *control_reg; member
262 ti_abb_rmw(regs->opp_sel_mask, info->opp_sel, abb->control_reg); in ti_abb_set_opp()
273 ti_abb_rmw(regs->opp_change_mask, 1, abb->control_reg); in ti_abb_set_opp()
725 abb->control_reg = abb->base + abb->regs->control_off; in ti_abb_probe()
728 abb->control_reg = devm_platform_ioremap_resource_byname(pdev, "control-address"); in ti_abb_probe()
729 if (IS_ERR(abb->control_reg)) in ti_abb_probe()
730 return PTR_ERR(abb->control_reg); in ti_abb_probe()
/linux-6.3-rc2/drivers/staging/fieldbus/anybuss/
A Darcx-anybus.c45 u8 control_reg; member
58 cd->control_reg &= ~rst_bit; in do_reset()
60 cd->control_reg |= rst_bit; in do_reset()
61 writeb(cd->control_reg, cd->cpld_base + CPLD_CONTROL); in do_reset()
/linux-6.3-rc2/drivers/i2c/busses/
A Di2c-mt65xx.c543 u16 control_reg; in mtk_i2c_init_hw() local
621 control_reg = I2C_CONTROL_ACKERR_DET_EN | in mtk_i2c_init_hw()
624 control_reg |= I2C_CONTROL_DMAACK_EN | I2C_CONTROL_ASYNC_MODE; in mtk_i2c_init_hw()
626 mtk_i2c_writew(i2c, control_reg, OFFSET_CONTROL); in mtk_i2c_init_hw()
991 u16 control_reg; in mtk_i2c_do_transfer() local
1031 control_reg = mtk_i2c_readw(i2c, OFFSET_CONTROL) & in mtk_i2c_do_transfer()
1034 control_reg |= I2C_CONTROL_RS; in mtk_i2c_do_transfer()
1037 control_reg |= I2C_CONTROL_DIR_CHANGE | I2C_CONTROL_RS; in mtk_i2c_do_transfer()
1039 mtk_i2c_writew(i2c, control_reg, OFFSET_CONTROL); in mtk_i2c_do_transfer()

Completed in 58 milliseconds

12