Searched refs:cp_hqd_pq_control (Results 1 – 22 of 22) sorted by relevance
| /linux-6.3-rc2/drivers/gpu/drm/amd/amdkfd/ |
| A D | kfd_mqd_manager_cik.c | 180 m->cp_hqd_pq_control = DEFAULT_RPTR_BLOCK_SIZE | in __update_mqd()
184 m->cp_hqd_pq_control |= PQ_ATC_EN; in __update_mqd()
192 m->cp_hqd_pq_control |= order_base_2(q->queue_size / 4) - 1; in __update_mqd()
202 m->cp_hqd_pq_control |= NO_UPDATE_RPTR; in __update_mqd()
350 m->cp_hqd_pq_control = DEFAULT_RPTR_BLOCK_SIZE | in update_mqd_hiq()
359 m->cp_hqd_pq_control |= order_base_2(q->queue_size / 4) - 1; in update_mqd_hiq()
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| A D | kfd_mqd_manager_v11.c | 192 m->cp_hqd_pq_control = 5 << CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT; in update_mqd()
193 m->cp_hqd_pq_control |= in update_mqd()
195 pr_debug("cp_hqd_pq_control 0x%x\n", m->cp_hqd_pq_control); in update_mqd()
233 m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK | in update_mqd()
302 m->cp_hqd_pq_control |= 1 << CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT | in init_mqd_hiq()
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| A D | kfd_mqd_manager_v10.c | 166 m->cp_hqd_pq_control = 5 << CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT; in update_mqd()
167 m->cp_hqd_pq_control |= in update_mqd()
169 pr_debug("cp_hqd_pq_control 0x%x\n", m->cp_hqd_pq_control); in update_mqd()
207 m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK | in update_mqd()
302 m->cp_hqd_pq_control |= 1 << CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT | in init_mqd_hiq()
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| A D | kfd_mqd_manager_v9.c | 216 m->cp_hqd_pq_control = 5 << CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT; in update_mqd()
217 m->cp_hqd_pq_control |= order_base_2(q->queue_size / 4) - 1; in update_mqd()
218 pr_debug("cp_hqd_pq_control 0x%x\n", m->cp_hqd_pq_control); in update_mqd()
257 m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK | in update_mqd()
365 m->cp_hqd_pq_control |= 1 << CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT | in init_mqd_hiq()
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| A D | kfd_mqd_manager_vi.c | 179 m->cp_hqd_pq_control = 5 << CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT | in __update_mqd()
182 m->cp_hqd_pq_control |= order_base_2(q->queue_size / 4) - 1; in __update_mqd()
183 pr_debug("cp_hqd_pq_control 0x%x\n", m->cp_hqd_pq_control); in __update_mqd()
226 m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK | in __update_mqd()
337 m->cp_hqd_pq_control |= 1 << CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT | in init_mqd_hiq()
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| /linux-6.3-rc2/drivers/gpu/drm/amd/include/ |
| A D | cik_structs.h | 96 uint32_t cp_hqd_pq_control; member
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| A D | vi_structs.h | 305 uint32_t cp_hqd_pq_control; member
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| A D | v9_structs.h | 305 uint32_t cp_hqd_pq_control; member
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| A D | v11_structs.h | 820 uint32_t cp_hqd_pq_control; // offset: 145 (0x91) member
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| A D | v10_structs.h | 822 uint32_t cp_hqd_pq_control; member
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| /linux-6.3-rc2/drivers/gpu/drm/amd/amdgpu/ |
| A D | gfx_v7_0.c | 2780 u32 cp_hqd_pq_control; member
2893 mqd->cp_hqd_pq_control = RREG32(mmCP_HQD_PQ_CONTROL); in gfx_v7_0_mqd_init()
2894 mqd->cp_hqd_pq_control &= in gfx_v7_0_mqd_init()
2898 mqd->cp_hqd_pq_control |= in gfx_v7_0_mqd_init()
2900 mqd->cp_hqd_pq_control |= in gfx_v7_0_mqd_init()
2903 mqd->cp_hqd_pq_control |= in gfx_v7_0_mqd_init()
2906 mqd->cp_hqd_pq_control &= in gfx_v7_0_mqd_init()
2910 mqd->cp_hqd_pq_control |= in gfx_v7_0_mqd_init()
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| A D | mes_v10_1.c | 699 mqd->cp_hqd_pq_control = tmp; in mes_v10_1_mqd_init()
775 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL, mqd->cp_hqd_pq_control);
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| A D | amdgpu_amdkfd_gfx_v11.c | 223 2 << REG_GET_FIELD(m->cp_hqd_pq_control, in hqd_load_v11()
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| A D | amdgpu_amdkfd_gfx_v10.c | 251 2 << REG_GET_FIELD(m->cp_hqd_pq_control, in kgd_hqd_load()
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| A D | mes_v11_0.c | 763 mqd->cp_hqd_pq_control = tmp; in mes_v11_0_mqd_init()
838 WREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL, mqd->cp_hqd_pq_control); in mes_v11_0_queue_init_register()
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| A D | amdgpu_amdkfd_gfx_v9.c | 265 2 << REG_GET_FIELD(m->cp_hqd_pq_control, in kgd_gfx_v9_hqd_load()
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| A D | amdgpu_amdkfd_gfx_v10_3.c | 238 2 << REG_GET_FIELD(m->cp_hqd_pq_control, in hqd_load_v10_3()
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| A D | gfx_v9_0.c | 3310 mqd->cp_hqd_pq_control = tmp; in gfx_v9_0_mqd_init()
3410 mqd->cp_hqd_pq_control); in gfx_v9_0_kiq_init_register()
3520 if (amdgpu_in_reset(adev) && tmp_mqd->cp_hqd_pq_control){ in gfx_v9_0_kiq_init_queue()
3566 if (!tmp_mqd->cp_hqd_pq_control || in gfx_v9_0_kcq_init_queue()
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| A D | gfx_v11_0.c | 3863 mqd->cp_hqd_pq_control = tmp; in gfx_v11_0_compute_mqd_init()
3980 mqd->cp_hqd_pq_control); in gfx_v11_0_kiq_init_register()
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| A D | gfx_v10_0.c | 6663 mqd->cp_hqd_pq_control = tmp; in gfx_v10_0_compute_mqd_init()
6762 mqd->cp_hqd_pq_control); in gfx_v10_0_kiq_init_register()
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| A D | gfx_v8_0.c | 4474 mqd->cp_hqd_pq_control = tmp; in gfx_v8_0_mqd_init()
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| /linux-6.3-rc2/drivers/gpu/drm/radeon/ |
| A D | cik.c | 4451 u32 cp_hqd_pq_control; member
4658 mqd->queue_state.cp_hqd_pq_control = RREG32(CP_HQD_PQ_CONTROL); in cik_cp_compute_resume()
4659 mqd->queue_state.cp_hqd_pq_control &= in cik_cp_compute_resume()
4662 mqd->queue_state.cp_hqd_pq_control |= in cik_cp_compute_resume()
4664 mqd->queue_state.cp_hqd_pq_control |= in cik_cp_compute_resume()
4667 mqd->queue_state.cp_hqd_pq_control |= BUF_SWAP_32BIT; in cik_cp_compute_resume()
4669 mqd->queue_state.cp_hqd_pq_control &= in cik_cp_compute_resume()
4671 mqd->queue_state.cp_hqd_pq_control |= in cik_cp_compute_resume()
4673 WREG32(CP_HQD_PQ_CONTROL, mqd->queue_state.cp_hqd_pq_control); in cik_cp_compute_resume()
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