Searched refs:ctrl_pol (Results 1 – 4 of 4) sorted by relevance
| /linux-6.3-rc2/drivers/gpu/drm/msm/disp/mdp4/ |
| A D | mdp4_dsi_encoder.c | 46 uint32_t dsi_hsync_skew, vsync_period, vsync_len, ctrl_pol; in mdp4_dsi_encoder_mode_set() local
54 ctrl_pol = 0; in mdp4_dsi_encoder_mode_set()
56 ctrl_pol |= MDP4_DSI_CTRL_POLARITY_HSYNC_LOW; in mdp4_dsi_encoder_mode_set()
58 ctrl_pol |= MDP4_DSI_CTRL_POLARITY_VSYNC_LOW; in mdp4_dsi_encoder_mode_set()
82 mdp4_write(mdp4_kms, REG_MDP4_DSI_CTRL_POLARITY, ctrl_pol); in mdp4_dsi_encoder_mode_set()
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| A D | mdp4_dtv_encoder.c | 45 uint32_t dtv_hsync_skew, vsync_period, vsync_len, ctrl_pol; in mdp4_dtv_encoder_mode_set() local
57 ctrl_pol = 0; in mdp4_dtv_encoder_mode_set()
59 ctrl_pol |= MDP4_DTV_CTRL_POLARITY_HSYNC_LOW; in mdp4_dtv_encoder_mode_set()
61 ctrl_pol |= MDP4_DTV_CTRL_POLARITY_VSYNC_LOW; in mdp4_dtv_encoder_mode_set()
89 mdp4_write(mdp4_kms, REG_MDP4_DTV_CTRL_POLARITY, ctrl_pol); in mdp4_dtv_encoder_mode_set()
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| A D | mdp4_lcdc_encoder.c | 220 uint32_t lcdc_hsync_skew, vsync_period, vsync_len, ctrl_pol; in mdp4_lcdc_encoder_mode_set() local
232 ctrl_pol = 0; in mdp4_lcdc_encoder_mode_set()
234 ctrl_pol |= MDP4_LCDC_CTRL_POLARITY_HSYNC_LOW; in mdp4_lcdc_encoder_mode_set()
236 ctrl_pol |= MDP4_LCDC_CTRL_POLARITY_VSYNC_LOW; in mdp4_lcdc_encoder_mode_set()
264 mdp4_write(mdp4_kms, REG_MDP4_LCDC_CTRL_POLARITY, ctrl_pol); in mdp4_lcdc_encoder_mode_set()
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| /linux-6.3-rc2/drivers/gpu/drm/msm/disp/mdp5/ |
| A D | mdp5_encoder.c | 39 uint32_t dtv_hsync_skew, vsync_period, vsync_len, ctrl_pol; in mdp5_vid_encoder_mode_set() local
49 ctrl_pol = 0; in mdp5_vid_encoder_mode_set()
54 ctrl_pol |= MDP5_INTF_POLARITY_CTL_HSYNC_LOW; in mdp5_vid_encoder_mode_set()
56 ctrl_pol |= MDP5_INTF_POLARITY_CTL_VSYNC_LOW; in mdp5_vid_encoder_mode_set()
117 mdp5_write(mdp5_kms, REG_MDP5_INTF_POLARITY_CTL(intf), ctrl_pol); in mdp5_vid_encoder_mode_set()
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