Searched refs:dcefclk (Results 1 – 7 of 7) sorted by relevance
344 smu->smu_table.boot_values.dcefclk = 0; in smu_v12_0_get_vbios_bootup_values()361 smu->smu_table.boot_values.dcefclk = 0; in smu_v12_0_get_vbios_bootup_values()382 &smu->smu_table.boot_values.dcefclk); in smu_v12_0_get_vbios_bootup_values()
626 smu->smu_table.boot_values.dcefclk = 0; in smu_v13_0_get_vbios_bootup_values()640 smu->smu_table.boot_values.dcefclk = 0; in smu_v13_0_get_vbios_bootup_values()655 smu->smu_table.boot_values.dcefclk = 0; in smu_v13_0_get_vbios_bootup_values()686 smu->smu_table.boot_values.dcefclk = smu_info_v4_0->bootup_dcefclk_10khz; in smu_v13_0_get_vbios_bootup_values()914 max_sustainable_clocks->dcef_clock = smu->smu_table.boot_values.dcefclk / 100; in smu_v13_0_init_max_sustainable_clocks()
557 smu->smu_table.boot_values.dcefclk = 0; in smu_v11_0_get_vbios_bootup_values()574 smu->smu_table.boot_values.dcefclk = 0; in smu_v11_0_get_vbios_bootup_values()595 &smu->smu_table.boot_values.dcefclk); in smu_v11_0_get_vbios_bootup_values()838 max_sustainable_clocks->dcef_clock = smu->smu_table.boot_values.dcefclk / 100; in smu_v11_0_init_max_sustainable_clocks()
1077 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100; in navi10_set_default_dpm_table()1095 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100; in navi10_set_default_dpm_table()1113 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100; in navi10_set_default_dpm_table()1131 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100; in navi10_set_default_dpm_table()
1062 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100; in sienna_cichlid_set_default_dpm_table()1080 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100; in sienna_cichlid_set_default_dpm_table()1098 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100; in sienna_cichlid_set_default_dpm_table()1116 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100; in sienna_cichlid_set_default_dpm_table()
291 uint32_t dcefclk; member
1336 smu->smu_table.boot_values.dcefclk / 100); in smu_smc_hw_setup()
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