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Searched refs:dev_priv (Results 1 – 25 of 271) sorted by relevance

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/linux-6.3-rc2/drivers/gpu/drm/i915/soc/
A Dintel_pch.c17 drm_WARN_ON(&dev_priv->drm, GRAPHICS_VER(dev_priv) != 5); in intel_pch_type()
33 !IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)); in intel_pch_type()
35 IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv)); in intel_pch_type()
40 !IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)); in intel_pch_type()
42 !IS_HSW_ULT(dev_priv) && !IS_BDW_ULT(dev_priv)); in intel_pch_type()
47 !IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)); in intel_pch_type()
49 IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv)); in intel_pch_type()
57 !IS_HSW_ULT(dev_priv) && !IS_BDW_ULT(dev_priv)); in intel_pch_type()
114 drm_WARN_ON(&dev_priv->drm, !IS_ICELAKE(dev_priv)); in intel_pch_type()
118 drm_WARN_ON(&dev_priv->drm, !IS_JSL_EHL(dev_priv)); in intel_pch_type()
[all …]
A Dintel_pch.h67 #define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type) argument
68 #define INTEL_PCH_ID(dev_priv) ((dev_priv)->pch_id) argument
69 #define HAS_PCH_MTP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_MTP) argument
70 #define HAS_PCH_DG2(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_DG2) argument
71 #define HAS_PCH_ADP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_ADP) argument
72 #define HAS_PCH_DG1(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_DG1) argument
73 #define HAS_PCH_TGP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_TGP) argument
74 #define HAS_PCH_ICP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_ICP) argument
75 #define HAS_PCH_CNP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CNP) argument
76 #define HAS_PCH_SPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_SPT) argument
[all …]
/linux-6.3-rc2/drivers/gpu/drm/i915/
A Di915_drv.h412 #define DRIVER_CAPS(dev_priv) (&(dev_priv)->caps) argument
534 #define IS_G4X(dev_priv) (IS_G45(dev_priv) || IS_GM45(dev_priv)) argument
735 #define IS_GEN9_LP(dev_priv) (GRAPHICS_VER(dev_priv) == 9 && IS_LP(dev_priv)) argument
736 #define IS_GEN9_BC(dev_priv) (GRAPHICS_VER(dev_priv) == 9 && !IS_LP(dev_priv)) argument
774 #define HAS_WT(dev_priv) HAS_EDRAM(dev_priv) argument
801 #define HAS_BROKEN_CS_TLB(dev_priv) (IS_I830(dev_priv) || IS_I845G(dev_priv)) argument
808 (IS_SKL_GT3(dev_priv) || IS_SKL_GT4(dev_priv))
825 #define HAS_CUR_FBC(dev_priv) (!HAS_GMCH(dev_priv) && DISPLAY_VER(dev_priv) >= 7) argument
827 #define HAS_IPS(dev_priv) (IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv)) argument
830 #define HAS_DP20(dev_priv) (IS_DG2(dev_priv) || DISPLAY_VER(dev_priv) >= 14) argument
[all …]
A Di915_irq.c190 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || in intel_hpd_init_pins()
200 else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) in intel_hpd_init_pins()
210 (!HAS_PCH_SPLIT(dev_priv) || HAS_PCH_NOP(dev_priv))) in intel_hpd_init_pins()
217 else if (HAS_PCH_CNP(dev_priv) || HAS_PCH_SPT(dev_priv)) in intel_hpd_init_pins()
219 else if (HAS_PCH_LPT(dev_priv) || HAS_PCH_CPT(dev_priv)) in intel_hpd_init_pins()
595 return IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv); in i915_has_asle()
992 if (DISPLAY_VER(dev_priv) >= 5 || IS_G4X(dev_priv)) in i9xx_pipe_crc_irq_handler()
1180 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) in i9xx_hpd_irq_ack()
2581 if (HAS_PCH_CPT(dev_priv) || HAS_PCH_LPT(dev_priv)) in ibx_irq_reset()
3320 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) in gen8_de_irq_postinstall()
[all …]
A Di915_driver.c165 pre |= IS_SKYLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x6; in intel_detect_preproduction_hw()
166 pre |= IS_BROXTON(dev_priv) && INTEL_REVID(dev_priv) < 0xA; in intel_detect_preproduction_hw()
167 pre |= IS_KABYLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x1; in intel_detect_preproduction_hw()
168 pre |= IS_GEMINILAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x3; in intel_detect_preproduction_hw()
169 pre |= IS_ICELAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x7; in intel_detect_preproduction_hw()
244 i915_drm_clients_init(&dev_priv->clients, dev_priv); in i915_driver_early_probe()
342 sanitize_gpu(dev_priv); in i915_driver_mmio_probe()
1494 if (drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_RUNTIME_PM(dev_priv))) in intel_runtime_suspend()
1569 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) in intel_runtime_suspend()
1583 if (drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_RUNTIME_PM(dev_priv))) in intel_runtime_resume()
[all …]
A Di915_suspend.c41 if (GRAPHICS_VER(dev_priv) == 2 && IS_MOBILE(dev_priv)) { in intel_save_swf()
43 dev_priv->regfile.saveSWF0[i] = intel_de_read(dev_priv, SWF0(i)); in intel_save_swf()
44 dev_priv->regfile.saveSWF1[i] = intel_de_read(dev_priv, SWF1(i)); in intel_save_swf()
47 dev_priv->regfile.saveSWF3[i] = intel_de_read(dev_priv, SWF3(i)); in intel_save_swf()
50 dev_priv->regfile.saveSWF1[i] = intel_de_read(dev_priv, SWF1(i)); in intel_save_swf()
53 dev_priv->regfile.saveSWF0[i] = intel_de_read(dev_priv, SWF0(i)); in intel_save_swf()
54 dev_priv->regfile.saveSWF1[i] = intel_de_read(dev_priv, SWF1(i)); in intel_save_swf()
57 dev_priv->regfile.saveSWF3[i] = intel_de_read(dev_priv, SWF3(i)); in intel_save_swf()
66 if (GRAPHICS_VER(dev_priv) == 2 && IS_MOBILE(dev_priv)) { in intel_restore_swf()
95 dev_priv->regfile.saveDSPARB = intel_de_read(dev_priv, DSPARB); in i915_save_display()
[all …]
A Dintel_pm.c338 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { in _intel_set_memory_cxsr()
342 } else if (IS_G4X(dev_priv) || IS_I965GM(dev_priv)) { in _intel_set_memory_cxsr()
355 } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv)) { in _intel_set_memory_cxsr()
428 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) in intel_set_memory_cxsr()
2424 if (IS_I915GM(dev_priv) || IS_I945GM(dev_priv)) in i9xx_update_wm()
2438 if (IS_I945G(dev_priv) || IS_I945GM(dev_priv)) in i9xx_update_wm()
3003 if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) in ilk_setup_wm_latency()
3279 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) in ilk_wm_lp_latency()
4078 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) in ilk_wm_get_hw_state()
4869 else if (IS_I85X(dev_priv) || IS_I865G(dev_priv)) in intel_init_clock_gating_hooks()
[all …]
/linux-6.3-rc2/drivers/gpu/drm/i915/display/
A Dintel_display_power_well.c403 drm_WARN_ON(&dev_priv->drm, !IS_ICELAKE(dev_priv)); in icl_combo_phy_aux_power_well_enable()
435 drm_WARN_ON(&dev_priv->drm, !IS_ICELAKE(dev_priv)); in icl_combo_phy_aux_power_well_disable()
595 if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv) && in hsw_power_well_enabled()
615 drm_WARN_ONCE(&dev_priv->drm, intel_irqs_enabled(dev_priv), in assert_can_enable_dc9()
629 drm_WARN_ONCE(&dev_priv->drm, intel_irqs_enabled(dev_priv), in assert_can_disable_dc9()
695 else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) in gen9_dc_mask()
822 if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv)) in gen9_enable_dc5()
849 if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv)) in skl_enable_dc6()
980 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) in gen9_disable_dc_states()
1160 val = intel_de_read(dev_priv, DSPCLK_GATE_D(dev_priv)); in vlv_init_display_clock_gating()
[all …]
A Dintel_fifo_underrun.c63 for_each_pipe(dev_priv, pipe) { in ivb_can_enable_err_int()
81 for_each_pipe(dev_priv, pipe) { in cpt_can_enable_serr_int()
122 intel_de_write(dev_priv, reg, in i9xx_set_fifo_underrun_reporting()
181 drm_err(&dev_priv->drm, in ivb_set_fifo_underrun_reporting()
271 drm_err(&dev_priv->drm, in cpt_set_fifo_underrun_reporting()
290 if (HAS_GMCH(dev_priv)) in __intel_set_cpu_fifo_underrun_reporting()
292 else if (IS_IRONLAKE(dev_priv) || IS_SANDYBRIDGE(dev_priv)) in __intel_set_cpu_fifo_underrun_reporting()
369 if (HAS_PCH_IBX(dev_priv)) in intel_set_pch_fifo_underrun_reporting()
402 if (HAS_GMCH(dev_priv) && in intel_cpu_fifo_underrun_irq_handler()
479 if (HAS_GMCH(dev_priv)) in intel_check_cpu_fifo_underruns()
[all …]
A Dintel_pch_refclk.c39 lpt_fdi_reset_mphy(dev_priv); in lpt_fdi_program_mphy()
117 mutex_lock(&dev_priv->sb_lock); in lpt_disable_iclkip()
189 lpt_disable_iclkip(dev_priv); in lpt_program_iclkip()
200 drm_dbg_kms(&dev_priv->drm, in lpt_program_iclkip()
204 mutex_lock(&dev_priv->sb_lock); in lpt_program_iclkip()
284 if (drm_WARN(&dev_priv->drm, HAS_PCH_LPT_LP(dev_priv) && in lpt_enable_clkout_dp()
413 if (IS_BROADWELL(dev_priv) && in spll_uses_pch_ssc()
432 if ((IS_BROADWELL(dev_priv) || IS_HSW_ULT(dev_priv)) && in wrpll_uses_pch_ssc()
527 if (HAS_PCH_IBX(dev_priv)) { in ilk_init_pch_refclk()
549 drm_dbg_kms(&dev_priv->drm, in ilk_init_pch_refclk()
[all …]
A Dintel_cdclk.c83 dev_priv->display.funcs.cdclk->get_cdclk(dev_priv, cdclk_config); in intel_cdclk_get_cdclk()
552 if (dev_priv->display.cdclk.hw.cdclk >= dev_priv->czclk_freq) { in vlv_program_pfi_credits()
1841 if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) && in _bxt_set_cdclk()
1983 if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) && in bxt_sanitize_cdclk()
2167 if (DISPLAY_VER(dev_priv) < 10 && !IS_BROXTON(dev_priv)) in intel_cdclk_can_cd2x_update()
2345 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) in intel_pixel_rate_to_cdclk()
2415 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && in intel_crtc_compute_min_cdclk()
2456 if (IS_TIGERLAKE(dev_priv) || IS_DG2(dev_priv)) { in intel_crtc_compute_min_cdclk()
2949 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) in intel_compute_max_dotclk()
3054 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) in intel_update_cdclk()
[all …]
A Dintel_fdi.c26 if (HAS_DDI(dev_priv)) { in assert_fdi_tx()
137 drm_dbg_kms(&dev_priv->drm, in ilk_check_fdi_lanes()
141 drm_dbg_kms(&dev_priv->drm, in ilk_check_fdi_lanes()
147 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { in ilk_check_fdi_lanes()
149 drm_dbg_kms(&dev_priv->drm, in ilk_check_fdi_lanes()
176 drm_dbg_kms(&dev_priv->drm, in ilk_check_fdi_lanes()
184 drm_dbg_kms(&dev_priv->drm, in ilk_check_fdi_lanes()
291 drm_WARN_ON(&dev_priv->drm, in cpt_set_fdi_bc_bifurcation()
294 drm_WARN_ON(&dev_priv->drm, in cpt_set_fdi_bc_bifurcation()
368 if (IS_IVYBRIDGE(dev_priv)) in intel_fdi_normal_train()
[all …]
A Dintel_pch_display.c118 drm_dbg_kms(&dev_priv->drm, in ibx_sanitize_pch_hdmi_port()
137 drm_dbg_kms(&dev_priv->drm, in ibx_sanitize_pch_dp_port()
176 intel_set_m_n(dev_priv, m_n, in intel_pch_transcoder_set_m1_n1()
187 intel_set_m_n(dev_priv, m_n, in intel_pch_transcoder_set_m2_n2()
198 intel_get_m_n(dev_priv, m_n, in intel_pch_transcoder_get_m1_n1()
209 intel_get_m_n(dev_priv, m_n, in intel_pch_transcoder_get_m2_n2()
253 if (HAS_PCH_CPT(dev_priv)) { in ilk_enable_pch_transcoder()
271 if (HAS_PCH_IBX(dev_priv)) { in ilk_enable_pch_transcoder()
328 if (HAS_PCH_CPT(dev_priv)) { in ilk_disable_pch_transcoder()
377 if (HAS_PCH_CPT(dev_priv)) { in ilk_pch_enable()
[all …]
A Dintel_hotplug.c165 drm_dbg_kms(&dev_priv->drm, in intel_hpd_irq_storm_detect()
169 drm_dbg_kms(&dev_priv->drm, in intel_hpd_irq_storm_detect()
199 drm_info(&dev_priv->drm, in intel_hpd_irq_storm_switch_to_polling()
241 drm_dbg(&dev_priv->drm, in intel_hpd_irq_storm_reenable_work()
497 drm_dbg(&dev_priv->drm, in intel_hpd_irq_handler()
526 drm_WARN_ONCE(&dev_priv->drm, !HAS_GMCH(dev_priv), in intel_hpd_irq_handler()
570 queue_work(dev_priv->display.hotplug.dp_wq, &dev_priv->display.hotplug.dig_port_work); in intel_hpd_irq_handler()
593 if (!HAS_DISPLAY(dev_priv)) in intel_hpd_init()
706 if (!HAS_DISPLAY(dev_priv)) in intel_hpd_poll_disable()
734 if (!HAS_DISPLAY(dev_priv)) in intel_hpd_cancel_work()
[all …]
A Dintel_display_power.c583 drm_WARN(&dev_priv->drm, in __intel_display_power_put_domain()
921 if (IS_DG2(dev_priv)) in get_allowed_dc_mask()
927 else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) in get_allowed_dc_mask()
939 mask = IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv) || in get_allowed_dc_mask()
956 drm_err(&dev_priv->drm, in get_allowed_dc_mask()
996 get_allowed_dc_mask(dev_priv, dev_priv->params.enable_dc); in intel_power_domains_init()
1115 if (IS_ALDERLAKE_P(dev_priv) || DISPLAY_VER(dev_priv) >= 14) in icl_mbus_init()
1416 intel_pch_reset_handshake(dev_priv, !HAS_PCH_NOP(dev_priv)); in skl_display_core_init()
1579 if (IS_DGFX(dev_priv) && !IS_DG1(dev_priv)) in tgl_bw_buddy_init()
1632 intel_pch_reset_handshake(dev_priv, !HAS_PCH_NOP(dev_priv)); in icl_display_core_init()
[all …]
A Dintel_combo_phy.c101 drm_dbg(&dev_priv->drm, in check_phy_reg()
120 drm_dbg_kms(&dev_priv->drm, in icl_verify_procmon_ref_values()
159 if (!has_phy_misc(dev_priv, phy)) in icl_combo_phy_enabled()
214 else if (IS_ALDERLAKE_S(dev_priv)) in phy_is_master()
216 else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) in phy_is_master()
231 if (DISPLAY_VER(dev_priv) >= 12) { in icl_combo_phy_verify_state()
249 if (IS_JSL_EHL(dev_priv)) { in icl_combo_phy_verify_state()
325 drm_dbg(&dev_priv->drm, in icl_combo_phys_init()
394 if (IS_TIGERLAKE(dev_priv) || IS_DG1(dev_priv)) { in icl_combo_phys_uninit()
400 drm_dbg_kms(&dev_priv->drm, in icl_combo_phys_uninit()
[all …]
A Dintel_dpio_phy.c309 drm_err(&dev_priv->drm, in bxt_ddi_phy_set_signal_levels()
336 drm_dbg(&dev_priv->drm, in bxt_ddi_phy_is_enabled()
343 drm_dbg(&dev_priv->drm, in bxt_ddi_phy_is_enabled()
379 dev_priv->display.state.bxt_phy_grc = bxt_get_grc(dev_priv, phy); in _bxt_ddi_phy_init()
387 drm_dbg(&dev_priv->drm, in _bxt_ddi_phy_init()
715 vlv_dpio_get(dev_priv); in chv_set_phy_signal_level()
796 vlv_dpio_put(dev_priv); in chv_set_phy_signal_level()
866 vlv_dpio_get(dev_priv); in chv_phy_pre_pll_enable()
921 vlv_dpio_put(dev_priv); in chv_phy_pre_pll_enable()
936 vlv_dpio_get(dev_priv); in chv_phy_pre_encoder_enable()
[all …]
A Dintel_lpe_audio.c80 #define HAS_LPE_AUDIO(dev_priv) ((dev_priv)->display.audio.lpe.platdev != NULL) argument
133 drm_err(&dev_priv->drm, in lpe_audio_platdev_create()
174 drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv)); in lpe_audio_irq_init()
187 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { in lpe_audio_detect()
197 drm_info(&dev_priv->drm, in lpe_audio_detect()
217 drm_dbg(&dev_priv->drm, "irq = %d\n", dev_priv->display.audio.lpe.irq); in lpe_audio_setup()
222 drm_err(&dev_priv->drm, in lpe_audio_setup()
228 dev_priv->display.audio.lpe.platdev = lpe_audio_platdev_create(dev_priv); in lpe_audio_setup()
232 drm_err(&dev_priv->drm, in lpe_audio_setup()
264 if (!HAS_LPE_AUDIO(dev_priv)) in intel_lpe_audio_irq_handler()
[all …]
A Dvlv_dsi.c304 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { in intel_dsi_compute_config()
653 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { in intel_dsi_port_enable()
803 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { in intel_dsi_pre_enable()
956 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { in intel_dsi_post_disable()
995 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { in intel_dsi_post_disable()
1274 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { in intel_dsi_get_config()
1470 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { in intel_dsi_prepare()
1617 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) in intel_dsi_unprepare()
1864 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) in vlv_dsi_init()
1890 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) in vlv_dsi_init()
[all …]
A Dvlv_dsi_regs.h111 #define _MIPIA_INTR_STAT (_MIPI_MMIO_BASE(dev_priv) + 0xb004)
112 #define _MIPIC_INTR_STAT (_MIPI_MMIO_BASE(dev_priv) + 0xb804)
114 #define _MIPIA_INTR_EN (_MIPI_MMIO_BASE(dev_priv) + 0xb008)
115 #define _MIPIC_INTR_EN (_MIPI_MMIO_BASE(dev_priv) + 0xb808)
213 #define _MIPIA_HBP_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb02c)
214 #define _MIPIC_HBP_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb82c)
217 #define _MIPIA_HFP_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb030)
218 #define _MIPIC_HFP_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb830)
229 #define _MIPIA_VBP_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb03c)
412 #define _MIPIA_CTRL (_MIPI_MMIO_BASE(dev_priv) + 0xb104)
[all …]
/linux-6.3-rc2/drivers/gpu/drm/vmwgfx/
A Dvmwgfx_drv.c433 dev_priv->enable_state = vmw_read(dev_priv, SVGA_REG_ENABLE); in vmw_device_init()
444 dev_priv->fifo = vmw_fifo_create(dev_priv); in vmw_device_init()
453 dev_priv->last_read_seqno = vmw_fence_read(dev_priv); in vmw_device_init()
525 dev_priv->cman = vmw_cmdbuf_man_create(dev_priv); in vmw_request_device()
850 dev_priv->drm.dev_private = dev_priv; in vmw_driver_load()
918 dev_priv->memory_size -= dev_priv->vram_size; in vmw_driver_load()
958 dev_priv->texture_max_width = vmw_read(dev_priv, in vmw_driver_load()
962 dev_priv->texture_max_height = vmw_read(dev_priv, in vmw_driver_load()
967 dev_priv->max_primary_mem = dev_priv->vram_size; in vmw_driver_load()
977 dev_priv->max_mob_size / 1024, dev_priv->max_mob_pages); in vmw_driver_load()
[all …]
A Dvmwgfx_irq.c144 vmw_update_seqno(dev_priv); in vmw_seqno_passed()
148 if (!vmw_has_fences(dev_priv) && vmw_fifo_idle(dev_priv, seqno)) in vmw_seqno_passed()
187 if (dev_priv->cman) { in vmw_fallback_wait()
249 vmw_write(dev_priv, SVGA_REG_IRQMASK, dev_priv->irq_mask); in vmw_generic_waiter_add()
260 vmw_write(dev_priv, SVGA_REG_IRQMASK, dev_priv->irq_mask); in vmw_generic_waiter_remove()
279 vmw_generic_waiter_add(dev_priv, vmw_irqflag_fence_goal(dev_priv), in vmw_goal_waiter_add()
285 vmw_generic_waiter_remove(dev_priv, vmw_irqflag_fence_goal(dev_priv), in vmw_goal_waiter_remove()
341 drm_err(&dev_priv->drm, in vmw_irq_install()
352 drm_err(&dev_priv->drm, in vmw_irq_install()
356 dev_priv->irqs[i] = ret; in vmw_irq_install()
[all …]
A Dvmwgfx_cmd.c46 if (!dev_priv->has_mob) in vmw_supports_3d()
102 if (!dev_priv->fifo_mem) in vmw_fifo_create()
130 vmw_fifo_mem_write(dev_priv, SVGA_FIFO_MAX, dev_priv->fifo_mem_size); in vmw_fifo_create()
143 drm_info(&dev_priv->drm, in vmw_fifo_create()
150 drm_warn(&dev_priv->drm, in vmw_fifo_create()
183 dev_priv->fifo = NULL; in vmw_fifo_destroy()
369 if (dev_priv->cman) in vmw_cmd_ctx_reserve()
473 if (dev_priv->cman) in vmw_cmd_commit()
488 if (dev_priv->cman) in vmw_cmd_commit_flush()
505 if (dev_priv->cman) in vmw_cmd_flush()
[all …]
/linux-6.3-rc2/drivers/gpu/drm/gma500/
A Dpsb_drv.c157 psb_spank(dev_priv); in psb_do_init()
186 if (dev_priv->mmu) { in psb_driver_unload()
191 (dev_priv->mmu), in psb_driver_unload()
248 pg = &dev_priv->gtt; in psb_driver_load()
252 dev_priv->num_pipe = dev_priv->ops->pipes; in psb_driver_load()
256 dev_priv->vdc_reg = in psb_driver_load()
286 dev_priv->aux_reg = dev_priv->vdc_reg; in psb_driver_load()
289 dev_priv->gmbus_reg = dev_priv->aux_reg; in psb_driver_load()
311 dev_priv->gmbus_reg = dev_priv->vdc_reg; in psb_driver_load()
341 if (!dev_priv->mmu) in psb_driver_load()
[all …]
A Dintel_bios.c55 dev_priv->edp.bpp = 18; in parse_edp()
67 dev_priv->edp.bpp = 18; in parse_edp()
70 dev_priv->edp.bpp = 24; in parse_edp()
73 dev_priv->edp.bpp = 30; in parse_edp()
84 dev_priv->edp.pps.t1_t3, dev_priv->edp.pps.t8, in parse_edp()
85 dev_priv->edp.pps.t9, dev_priv->edp.pps.t10, in parse_edp()
92 dev_priv->edp.lanes = 1; in parse_edp()
95 dev_priv->edp.lanes = 2; in parse_edp()
99 dev_priv->edp.lanes = 4; in parse_edp()
103 dev_priv->edp.lanes, dev_priv->edp.rate, dev_priv->edp.bpp); in parse_edp()
[all …]

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