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Searched refs:div4_clks (Results 1 – 15 of 15) sorted by relevance

/linux-6.3-rc2/arch/sh/kernel/cpu/sh4a/
A Dclock-sh7734.c72 struct clk div4_clks[DIV4_NR] = { variable
141 [MSTP009] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 9, 0),
142 [MSTP008] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 8, 0),
143 [MSTP007] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 7, 0),
184 CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
185 CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_S]),
186 CLKDEV_CON_ID("ddr_clk", &div4_clks[DIV4_M]),
187 CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]),
188 CLKDEV_CON_ID("shyway_clk1", &div4_clks[DIV4_S1]),
189 CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
[all …]
A Dclock-sh7723.c114 struct clk div4_clks[DIV4_NR] = { variable
160 [HWBLK_SCIF0] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 9, 0),
161 [HWBLK_SCIF1] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 8, 0),
162 [HWBLK_SCIF2] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 7, 0),
202 CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
203 CLKDEV_CON_ID("umem_clk", &div4_clks[DIV4_U]),
204 CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),
205 CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]),
206 CLKDEV_CON_ID("b3_clk", &div4_clks[DIV4_B3]),
207 CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
[all …]
A Dclock-sh7343.c108 struct clk div4_clks[DIV4_NR] = { variable
155 [MSTP007] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 7, 0),
156 [MSTP006] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 6, 0),
157 [MSTP005] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 5, 0),
193 CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
194 CLKDEV_CON_ID("umem_clk", &div4_clks[DIV4_U]),
195 CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),
196 CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]),
197 CLKDEV_CON_ID("b3_clk", &div4_clks[DIV4_B3]),
199 CLKDEV_CON_ID("siua_clk", &div4_clks[DIV4_SIUA]),
[all …]
A Dclock-sh7366.c111 struct clk div4_clks[DIV4_NR] = { variable
158 [MSTP007] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 7, 0),
159 [MSTP006] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 6, 0),
160 [MSTP005] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 5, 0),
191 CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
192 CLKDEV_CON_ID("umem_clk", &div4_clks[DIV4_U]),
193 CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),
194 CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]),
195 CLKDEV_CON_ID("b3_clk", &div4_clks[DIV4_B3]),
197 CLKDEV_CON_ID("siua_clk", &div4_clks[DIV4_SIUA]),
[all …]
A Dclock-sh7724.c153 struct clk div4_clks[DIV4_NR] = { variable
220 [HWBLK_SCIF0] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 9, 0),
221 [HWBLK_SCIF1] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 8, 0),
222 [HWBLK_SCIF2] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 7, 0),
223 [HWBLK_SCIF3] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 6, 0),
268 CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
269 CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),
270 CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]),
271 CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
272 CLKDEV_CON_ID("vpu_clk", &div4_clks[DIV4_M1]),
[all …]
A Dclock-sh7785.c69 struct clk div4_clks[DIV4_NR] = { variable
103 [MSTP009] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 9, 0),
122 CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
123 CLKDEV_CON_ID("du_clk", &div4_clks[DIV4_DU]),
124 CLKDEV_CON_ID("ga_clk", &div4_clks[DIV4_GA]),
125 CLKDEV_CON_ID("ddr_clk", &div4_clks[DIV4_DDR]),
126 CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]),
127 CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),
128 CLKDEV_CON_ID("umem_clk", &div4_clks[DIV4_U]),
129 CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
[all …]
A Dclock-sh7786.c70 struct clk div4_clks[DIV4_NR] = { variable
92 [MSTP029] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 29, 0),
108 [MSTP009] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 9, 0),
109 [MSTP008] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 8, 0),
131 CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
132 CLKDEV_CON_ID("du_clk", &div4_clks[DIV4_DU]),
133 CLKDEV_CON_ID("ddr_clk", &div4_clks[DIV4_DDR]),
134 CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]),
135 CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),
136 CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
[all …]
A Dclock-shx3.c64 struct clk div4_clks[DIV4_NR] = { variable
87 [MSTP009] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 9, 0),
88 [MSTP008] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 8, 0),
89 [MSTP003] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 3, 0),
106 CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
107 CLKDEV_CON_ID("shywaya_clk", &div4_clks[DIV4_SHA]),
108 CLKDEV_CON_ID("ddr_clk", &div4_clks[DIV4_DDR]),
109 CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]),
110 CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),
111 CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
[all …]
A Dclock-sh7722.c113 struct clk div4_clks[DIV4_NR] = { variable
148 [HWBLK_SCIF0] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 7, 0),
149 [HWBLK_SCIF1] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 6, 0),
150 [HWBLK_SCIF2] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 5, 0),
177 CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
178 CLKDEV_CON_ID("umem_clk", &div4_clks[DIV4_U]),
179 CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),
180 CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]),
181 CLKDEV_CON_ID("b3_clk", &div4_clks[DIV4_B3]),
182 CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
[all …]
A Dclock-sh7757.c65 struct clk div4_clks[DIV4_NR] = { variable
85 [MSTP004] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 4, 0),
86 [MSTP000] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 0, 0),
89 [MSTP127] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 27, 0),
90 [MSTP114] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 14, 0),
95 [MSTP103] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 3, 0),
96 [MSTP102] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 2, 0),
108 CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
109 CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),
110 CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
[all …]
/linux-6.3-rc2/arch/sh/kernel/cpu/sh2a/
A Dclock-sh7264.c81 struct clk div4_clks[DIV4_NR] = { variable
93 [MSTP77] = SH_CLK_MSTP8(&div4_clks[DIV4_P], STBCR7, 7, 0), /* SCIF */
94 [MSTP74] = SH_CLK_MSTP8(&div4_clks[DIV4_P], STBCR7, 4, 0), /* VDC */
95 [MSTP72] = SH_CLK_MSTP8(&div4_clks[DIV4_P], STBCR7, 2, 0), /* CMT */
96 [MSTP60] = SH_CLK_MSTP8(&div4_clks[DIV4_P], STBCR6, 0, 0), /* USB */
97 [MSTP35] = SH_CLK_MSTP8(&div4_clks[DIV4_P], STBCR3, 6, 0), /* MTU2 */
98 [MSTP34] = SH_CLK_MSTP8(&div4_clks[DIV4_P], STBCR3, 4, 0), /* SDHI0 */
100 [MSTP32] = SH_CLK_MSTP8(&div4_clks[DIV4_P], STBCR3, 2, 0), /* ADC */
111 CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
112 CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
[all …]
A Dclock-sh7269.c109 struct clk div4_clks[DIV4_NR] = { variable
146 CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
147 CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]),
175 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table); in arch_clk_init()
/linux-6.3-rc2/drivers/clk/renesas/
A Dclk-r8a73a4.c41 static struct div4_clk div4_clks[] = { variable
165 for (c = div4_clks; c->name; c++) { in r8a73a4_cpg_register_clock()
A Dclk-r8a7740.c38 static struct div4_clk div4_clks[] = { variable
121 for (c = div4_clks; c->name; c++) { in r8a7740_cpg_register_clock()
A Dclk-sh73a0.c46 static const struct div4_clk div4_clks[] = { variable
137 for (c = div4_clks; c->name; c++) { in sh73a0_cpg_register_clock()

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