| /linux-6.3-rc2/drivers/gpu/drm/radeon/ |
| A D | rv740_dpm.c | 123 struct atom_clock_dividers dividers; in rv740_populate_sclk_value() local
136 engine_clock, false, ÷rs); in rv740_populate_sclk_value()
140 reference_divider = 1 + dividers.ref_div; in rv740_populate_sclk_value()
147 spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div); in rv740_populate_sclk_value()
198 struct atom_clock_dividers dividers; in rv740_populate_mclk_value() local
204 memory_clock, false, ÷rs); in rv740_populate_mclk_value()
215 mpll_ad_func_cntl |= CLKR(dividers.ref_div); in rv740_populate_mclk_value()
221 if (dividers.vco_mode) in rv740_populate_mclk_value()
232 mpll_dq_func_cntl |= CLKR(dividers.ref_div); in rv740_populate_mclk_value()
238 if (dividers.vco_mode) in rv740_populate_mclk_value()
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| A D | rv730_dpm.c | 42 struct atom_clock_dividers dividers; in rv730_populate_sclk_value() local
55 engine_clock, false, ÷rs); in rv730_populate_sclk_value()
59 reference_divider = 1 + dividers.ref_div; in rv730_populate_sclk_value()
61 if (dividers.enable_post_div) in rv730_populate_sclk_value()
63 (dividers.post_div & 0xf) + 2; in rv730_populate_sclk_value()
72 if (dividers.enable_post_div) in rv730_populate_sclk_value()
128 struct atom_clock_dividers dividers; in rv730_populate_mclk_value() local
139 if (dividers.enable_post_div) in rv730_populate_mclk_value()
141 (dividers.post_div & 0xf) + 2; in rv730_populate_mclk_value()
146 if (dividers.enable_post_div) in rv730_populate_mclk_value()
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| A D | rv6xx_dpm.c | 145 clock, false, ÷rs); in rv6xx_convert_clock_to_stepping()
149 if (dividers.enable_post_div) in rv6xx_convert_clock_to_stepping()
150 step->post_divider = 2 + (dividers.post_div & 0xF) + (dividers.post_div >> 4); in rv6xx_convert_clock_to_stepping()
530 (dividers->ref_div + 1); in rv6xx_calculate_vco_frequency()
610 if (dividers.enable_post_div) in rv6xx_program_mclk_stepping_entry()
646 *dividers = req_dividers; in rv6xx_find_memory_clock_with_highest_vco()
666 ÷rs, in rv6xx_program_mclk_spread_spectrum_parameters()
672 ÷rs, in rv6xx_program_mclk_spread_spectrum_parameters()
678 ÷rs, in rv6xx_program_mclk_spread_spectrum_parameters()
1958 0, false, ÷rs); in rv6xx_dpm_init()
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| A D | rv770_dpm.c | 334 post_divider = dividers->post_div; in rv770_calculate_fractional_mpll_feedback_divider()
404 struct atom_clock_dividers dividers; in rv770_populate_mclk_value() local
416 if ((dividers.ref_div < 1) || (dividers.ref_div > 5)) in rv770_populate_mclk_value()
421 ÷rs, &clkf, &clkfrac); in rv770_populate_mclk_value()
440 if (dividers.vco_mode) in rv770_populate_mclk_value()
449 ÷rs, &clkf, &clkfrac); in rv770_populate_mclk_value()
468 if (dividers.vco_mode) in rv770_populate_mclk_value()
514 if (dividers.enable_post_div) in rv770_populate_sclk_value()
515 post_divider = (0x0f & (dividers.post_div >> 4)) + (0x0f & dividers.post_div) + 2; in rv770_populate_sclk_value()
523 if (dividers.enable_post_div) in rv770_populate_sclk_value()
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| A D | cypress_dpm.c | 493 struct atom_clock_dividers dividers; in cypress_populate_mclk_value() local
500 memory_clock, strobe_mode, ÷rs); in cypress_populate_mclk_value()
508 dividers.post_div = 1; in cypress_populate_mclk_value()
518 mpll_ad_func_cntl |= CLKR(dividers.ref_div); in cypress_populate_mclk_value()
524 if (dividers.vco_mode) in cypress_populate_mclk_value()
535 mpll_dq_func_cntl |= CLKR(dividers.ref_div); in cypress_populate_mclk_value()
546 if (dividers.vco_mode) in cypress_populate_mclk_value()
562 (0x4000 * dividers.whole_fb_div + 0x800 * dividers.frac_fb_div) / (clk_s * 625); in cypress_populate_mclk_value()
2024 struct atom_clock_dividers dividers; in cypress_dpm_init() local
2055 0, false, ÷rs); in cypress_dpm_init()
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| A D | rs780_dpm.c | 78 struct atom_clock_dividers dividers; in rs780_initialize_dpm_power_state() local
83 default_state->sclk_low, false, ÷rs); in rs780_initialize_dpm_power_state()
87 r600_engine_clock_entry_set_reference_divider(rdev, 0, dividers.ref_div); in rs780_initialize_dpm_power_state()
88 r600_engine_clock_entry_set_feedback_divider(rdev, 0, dividers.fb_div); in rs780_initialize_dpm_power_state()
89 r600_engine_clock_entry_set_post_divider(rdev, 0, dividers.post_div); in rs780_initialize_dpm_power_state()
91 if (dividers.enable_post_div) in rs780_initialize_dpm_power_state()
1033 struct atom_clock_dividers dividers; in rs780_dpm_force_performance_level() local
1044 ps->sclk_high, false, ÷rs); in rs780_dpm_force_performance_level()
1048 rs780_force_fbdiv(rdev, dividers.fb_div); in rs780_dpm_force_performance_level()
1051 ps->sclk_low, false, ÷rs); in rs780_dpm_force_performance_level()
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| A D | radeon_atombios.c | 2856 dividers->post_div = args.v1.ucPostDiv; in radeon_atom_get_clock_dividers()
2857 dividers->fb_div = args.v1.ucFbDiv; in radeon_atom_get_clock_dividers()
2858 dividers->enable_post_div = true; in radeon_atom_get_clock_dividers()
2870 dividers->post_div = args.v2.ucPostDiv; in radeon_atom_get_clock_dividers()
2872 dividers->ref_div = args.v2.ucAction; in radeon_atom_get_clock_dividers()
2878 dividers->enable_post_div = (dividers->fb_div & 1) ? true : false; in radeon_atom_get_clock_dividers()
2885 dividers->post_div = args.v3.ucPostDiv; in radeon_atom_get_clock_dividers()
2892 dividers->ref_div = args.v3.ucRefDiv; in radeon_atom_get_clock_dividers()
2905 dividers->post_div = args.v5.ucPostDiv; in radeon_atom_get_clock_dividers()
2912 dividers->ref_div = args.v5.ucRefDiv; in radeon_atom_get_clock_dividers()
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| /linux-6.3-rc2/drivers/gpu/drm/amd/display/modules/color/ |
| A D | color_gamma.c | 286 struct dividers { struct
1176 struct dividers dividers) in scale_gamma() argument
1212 dividers.divider1); in scale_gamma()
1239 struct dividers dividers) in scale_gamma_dx() argument
1307 struct dividers dividers) in scale_user_regamma_ramp() argument
1463 struct dividers dividers) in build_evenly_distributed_points() argument
1817 struct dividers dividers; in calculate_user_regamma_ramp() local
1881 struct dividers dividers; in mod_color_calculate_degamma_params() local
1941 dividers); in mod_color_calculate_degamma_params()
2122 struct dividers dividers; in mod_color_calculate_regamma_params() local
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| /linux-6.3-rc2/Documentation/devicetree/bindings/clock/ti/ |
| A D | divider.txt | 30 Additionally an array of valid dividers may be supplied like so:
32 ti,dividers = <4>, <8>, <0>, <16>;
45 unless the divider array is provided, min and max dividers. Optionally
63 - ti,dividers : array of integers defining divisors
68 if ti,dividers is not defined.
70 only valid if ti,dividers is not defined.
72 only valid if ti,dividers is not defined.
116 ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>;
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| /linux-6.3-rc2/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ |
| A D | ppatomctrl.c | 426 dividers->pll_post_divider = in atomctrl_get_engine_pll_dividers_vi()
428 dividers->real_clock = in atomctrl_get_engine_pll_dividers_vi()
433 dividers->ul_fb_div.ul_fb_div = in atomctrl_get_engine_pll_dividers_vi()
436 dividers->uc_pll_ref_div = in atomctrl_get_engine_pll_dividers_vi()
438 dividers->uc_pll_post_div = in atomctrl_get_engine_pll_dividers_vi()
440 dividers->uc_pll_cntl_flag = in atomctrl_get_engine_pll_dividers_vi()
496 dividers->pll_post_divider = in atomctrl_get_dfs_pll_dividers_vi()
498 dividers->real_clock = in atomctrl_get_dfs_pll_dividers_vi()
506 dividers->uc_pll_ref_div = in atomctrl_get_dfs_pll_dividers_vi()
508 dividers->uc_pll_post_div = in atomctrl_get_dfs_pll_dividers_vi()
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| A D | ppatomctrl.h | 308 …dividers_vi(struct pp_hwmgr *hwmgr, uint32_t clock_value, pp_atomctrl_clock_dividers_vi *dividers);
309 …dividers_vi(struct pp_hwmgr *hwmgr, uint32_t clock_value, pp_atomctrl_clock_dividers_vi *dividers);
318 pp_atomctrl_clock_dividers_kong *dividers);
323 …dividers_ai(struct pp_hwmgr *hwmgr, uint32_t clock_value, pp_atomctrl_clock_dividers_ai *dividers);
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| A D | ppatomfwctrl.c | 248 struct pp_atomfwctrl_clock_dividers_soc15 *dividers) in pp_atomfwctrl_get_gpu_pll_dividers_vega10() argument
266 dividers->ulClock = le32_to_cpu(pll_output->gpuclock_10khz); in pp_atomfwctrl_get_gpu_pll_dividers_vega10()
267 dividers->ulDid = le32_to_cpu(pll_output->dfs_did); in pp_atomfwctrl_get_gpu_pll_dividers_vega10()
268 dividers->ulPll_fb_mult = le32_to_cpu(pll_output->pll_fb_mult); in pp_atomfwctrl_get_gpu_pll_dividers_vega10()
269 dividers->ulPll_ss_fbsmult = le32_to_cpu(pll_output->pll_ss_fbsmult); in pp_atomfwctrl_get_gpu_pll_dividers_vega10()
270 dividers->usPll_ss_slew_frac = le16_to_cpu(pll_output->pll_ss_slew_frac); in pp_atomfwctrl_get_gpu_pll_dividers_vega10()
271 dividers->ucPll_ss_enable = pll_output->pll_ss_enable; in pp_atomfwctrl_get_gpu_pll_dividers_vega10()
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| /linux-6.3-rc2/drivers/clk/baikal-t1/ |
| A D | Kconfig | 12 configurable and fixed clock dividers. Enable this option to be able
27 CPUs, DDR, etc.) or passed over the clock dividers to be only
35 Enable this to support the CCU dividers used to distribute clocks
37 SoC. CCU dividers can be either configurable or with fixed divider,
38 either gateable or ungateable. Some of the CCU dividers can be as well
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| /linux-6.3-rc2/Documentation/devicetree/bindings/clock/ |
| A D | baikal,bt1-ccu-div.yaml | 19 by means of an embedded into CCU PLLs and gateable/non-gateable dividers. The
26 3) AXI-bus clock dividers (AXI) - described in this binding file.
27 4) System devices reference clock dividers (SYS) - described in this binding
51 then passed over CCU dividers to create signals required for the target clock
52 domain (like AXI-bus or System Device consumers). The dividers have the
71 peculiarities the dividers may lack of some functionality depicted on the
76 The clock dividers, which output clock is then consumed by the SoC individual
78 Similarly the dividers with output clocks utilized as AXI-bus reference clocks
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| A D | dove-divider-clock.txt | 3 Marvell Dove has a 2GHz PLL, which feeds into a set of dividers to provide
4 high speed clocks for a number of peripherals. These dividers are part of
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| A D | baikal,bt1-ccu-pll.yaml | 19 by means of PLLs and gateable/non-gateable dividers embedded into the CCU.
24 3) AXI-bus clock dividers (AXI).
25 4) System devices reference clock dividers (SYS).
73 the binding supports the PLL dividers configuration in accordance with a
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| A D | brcm,bcm2835-cprman.txt | 8 oscillator, a level of PLL dividers that produce channels off of the
12 the PLL dividers directly.
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| /linux-6.3-rc2/drivers/gpu/drm/amd/amdgpu/ |
| A D | amdgpu_atombios.c | 1000 struct atom_clock_dividers *dividers) in amdgpu_atombios_get_clock_dividers() argument
1023 dividers->post_div = args.v3.ucPostDiv; in amdgpu_atombios_get_clock_dividers()
1030 dividers->ref_div = args.v3.ucRefDiv; in amdgpu_atombios_get_clock_dividers()
1031 dividers->vco_mode = (args.v3.ucCntlFlag & in amdgpu_atombios_get_clock_dividers()
1043 dividers->post_div = args.v5.ucPostDiv; in amdgpu_atombios_get_clock_dividers()
1050 dividers->ref_div = args.v5.ucRefDiv; in amdgpu_atombios_get_clock_dividers()
1051 dividers->vco_mode = (args.v5.ucCntlFlag & in amdgpu_atombios_get_clock_dividers()
1061 dividers->post_divider = dividers->post_div = args.v4.ucPostDiv; in amdgpu_atombios_get_clock_dividers()
1074 dividers->ref_div = args.v6_out.ucPllRefDiv; in amdgpu_atombios_get_clock_dividers()
1075 dividers->post_div = args.v6_out.ucPllPostDiv; in amdgpu_atombios_get_clock_dividers()
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| A D | amdgpu_atombios.h | 161 struct atom_clock_dividers *dividers);
209 struct atom_clock_dividers *dividers);
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| /linux-6.3-rc2/drivers/gpu/drm/amd/pm/powerplay/smumgr/ |
| A D | polaris10_smumgr.c | 895 struct pp_atomctrl_clock_dividers_ai dividers; in polaris10_calculate_sclk_params() local
906 sclk_setting->Fcw_int = dividers.usSclk_fcw_int; in polaris10_calculate_sclk_params()
913 sclk_setting->SSc_En = dividers.ucSscEnable; in polaris10_calculate_sclk_params()
1058 pp_atomctrl_clock_dividers_vi dividers; in polaris10_populate_all_graphic_levels() local
1085 ÷rs); in polaris10_populate_all_graphic_levels()
1092 dividers.pll_post_divider - 1 : dividers.pll_post_divider, in polaris10_populate_all_graphic_levels()
1370 struct pp_atomctrl_clock_dividers_vi dividers; in polaris10_populate_smc_vce_level() local
1402 table->VceLevel[count].Frequency, ÷rs); in polaris10_populate_smc_vce_level()
1420 struct pp_atomctrl_clock_dividers_vi dividers; in polaris10_populate_smc_samu_level() local
1525 struct pp_atomctrl_clock_dividers_vi dividers; in polaris10_populate_smc_uvd_level() local
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| A D | vegam_smumgr.c | 725 struct pp_atomctrl_clock_dividers_ai dividers; in vegam_calculate_sclk_params() local
736 sclk_setting->Fcw_int = dividers.usSclk_fcw_int; in vegam_calculate_sclk_params()
737 sclk_setting->Fcw_frac = dividers.usSclk_fcw_frac; in vegam_calculate_sclk_params()
739 sclk_setting->PllRange = dividers.ucSclkPllRange; in vegam_calculate_sclk_params()
743 sclk_setting->SSc_En = dividers.ucSscEnable; in vegam_calculate_sclk_params()
744 sclk_setting->Fcw1_int = dividers.usSsc_fcw1_int; in vegam_calculate_sclk_params()
1200 struct pp_atomctrl_clock_dividers_vi dividers; in vegam_populate_smc_vce_level() local
1232 table->VceLevel[count].Frequency, ÷rs); in vegam_populate_smc_vce_level()
1313 struct pp_atomctrl_clock_dividers_vi dividers; in vegam_populate_smc_uvd_level() local
1931 pp_atomctrl_clock_dividers_vi dividers; in vegam_init_smc_table() local
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| A D | fiji_smumgr.c | 859 struct pp_atomctrl_clock_dividers_vi dividers; in fiji_calculate_sclk_params() local
879 ref_divider = 1 + dividers.uc_pll_ref_div; in fiji_calculate_sclk_params()
886 SPLL_REF_DIV, dividers.uc_pll_ref_div); in fiji_calculate_sclk_params()
888 SPLL_PDIV_A, dividers.uc_pll_post_div); in fiji_calculate_sclk_params()
1303 struct pp_atomctrl_clock_dividers_vi dividers; in fiji_populate_smc_acpi_level() local
1334 table->ACPILevel.SclkFrequency, ÷rs); in fiji_populate_smc_acpi_level()
1423 struct pp_atomctrl_clock_dividers_vi dividers; in fiji_populate_smc_vce_level() local
1444 table->VceLevel[count].Frequency, ÷rs); in fiji_populate_smc_vce_level()
1462 struct pp_atomctrl_clock_dividers_vi dividers; in fiji_populate_smc_acp_level() local
1481 table->AcpLevel[count].Frequency, ÷rs); in fiji_populate_smc_acp_level()
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| /linux-6.3-rc2/Documentation/devicetree/bindings/arm/mediatek/ |
| A D | mediatek,mt8186-sys-clock.yaml | 15 dividers -->
21 The topckgen provides dividers and muxes which provide the clock source to other IP blocks.
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| A D | mediatek,mt8195-sys-clock.yaml | 15 dividers -->
21 The topckgen provides dividers and muxes which provide the clock source to other IP blocks.
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| /linux-6.3-rc2/arch/arm/boot/dts/ |
| A D | omap2420-clocks.dtsi | 79 ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>, <0>, <0>, <0>, <12>;
262 ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>, <0>, <0>, <0>, <12>;
266 ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>;
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