| /linux-6.3-rc2/drivers/gpu/drm/i915/display/ |
| A D | intel_dp_link_training.c | 41 enum drm_dp_phy dp_phy) in intel_dp_lttpr_phy_caps() argument
48 enum drm_dp_phy dp_phy) in intel_dp_read_lttpr_phy_caps() argument
57 drm_dp_phy_name(dp_phy)); in intel_dp_read_lttpr_phy_caps()
64 drm_dp_phy_name(dp_phy), in intel_dp_read_lttpr_phy_caps()
371 enum drm_dp_phy dp_phy, in intel_dp_get_lane_adjust_train() argument
409 enum drm_dp_phy dp_phy, in intel_dp_get_adjust_train() argument
451 enum drm_dp_phy dp_phy, in intel_dp_set_link_train() argument
531 enum drm_dp_phy dp_phy) in intel_dp_set_signal_levels() argument
561 enum drm_dp_phy dp_phy, in intel_dp_reset_link_train() argument
778 drm_dp_phy_name(dp_phy)); in intel_dp_link_training_clock_recovery()
[all …]
|
| A D | intel_dp_link_training.h | 18 enum drm_dp_phy dp_phy,
22 enum drm_dp_phy dp_phy,
26 enum drm_dp_phy dp_phy);
33 intel_dp_dump_link_status(struct intel_dp *intel_dp, enum drm_dp_phy dp_phy,
|
| /linux-6.3-rc2/drivers/phy/mediatek/ |
| A D | phy-mtk-dp.c | 87 struct mtk_dp_phy *dp_phy = phy_get_drvdata(phy); in mtk_dp_phy_init() local
111 struct mtk_dp_phy *dp_phy = phy_get_drvdata(phy); in mtk_dp_phy_configure() local
134 regmap_write(dp_phy->regs, MTK_DP_PHY_DIG_BIT_RATE, val); in mtk_dp_phy_configure()
145 struct mtk_dp_phy *dp_phy = phy_get_drvdata(phy); in mtk_dp_phy_reset() local
147 regmap_update_bits(dp_phy->regs, MTK_DP_PHY_DIG_SW_RST, in mtk_dp_phy_reset()
150 regmap_update_bits(dp_phy->regs, MTK_DP_PHY_DIG_SW_RST, in mtk_dp_phy_reset()
166 struct mtk_dp_phy *dp_phy; in mtk_dp_phy_probe() local
175 dp_phy = devm_kzalloc(dev, sizeof(*dp_phy), GFP_KERNEL); in mtk_dp_phy_probe()
176 if (!dp_phy) in mtk_dp_phy_probe()
179 dp_phy->regs = regs; in mtk_dp_phy_probe()
[all …]
|
| /linux-6.3-rc2/include/drm/display/ |
| A D | drm_dp.h | 1384 #define DP_LTTPR_BASE(dp_phy) \ argument
1386 ((dp_phy) - DP_PHY_LTTPR1))
1388 #define DP_LTTPR_REG(dp_phy, lttpr1_reg) \ argument
1392 #define DP_TRAINING_PATTERN_SET_PHY_REPEATER(dp_phy) \ argument
1396 #define DP_TRAINING_LANE0_SET_PHY_REPEATER(dp_phy) \ argument
1416 #define DP_LANE0_1_STATUS_PHY_REPEATER(dp_phy) \ argument
1431 #define DP_FEC_BASE(dp_phy) \ argument
1433 ((dp_phy) - DP_PHY_LTTPR1)))
1435 #define DP_FEC_REG(dp_phy, fec1_reg) \ argument
1439 #define DP_FEC_STATUS_PHY_REPEATER(dp_phy) \ argument
[all …]
|
| A D | drm_dp_helper.h | 48 enum drm_dp_phy dp_phy, bool uhbr);
50 enum drm_dp_phy dp_phy, bool uhbr);
72 const char *drm_dp_phy_name(enum drm_dp_phy dp_phy);
485 enum drm_dp_phy dp_phy,
542 enum drm_dp_phy dp_phy,
|
| /linux-6.3-rc2/Documentation/devicetree/bindings/clock/ |
| A D | qcom,sc7180-dispcc.yaml | 74 <&dp_phy 0>,
75 <&dp_phy 1>;
|
| A D | qcom,dispcc-sm6350.yaml | 74 <&dp_phy 0>,
75 <&dp_phy 1>;
|
| A D | qcom,dispcc-sm6125.yaml | 73 <&dp_phy 0>,
74 <&dp_phy 1>,
|
| A D | qcom,sc7280-dispcc.yaml | 78 <&dp_phy 0>,
79 <&dp_phy 1>,
|
| A D | qcom,sdm845-dispcc.yaml | 86 <&dp_phy 0>,
87 <&dp_phy 1>;
|
| A D | qcom,dispcc-sm8x50.yaml | 94 <&dp_phy 0>,
95 <&dp_phy 1>;
|
| /linux-6.3-rc2/drivers/gpu/drm/display/ |
| A D | drm_dp_helper.c | 285 enum drm_dp_phy dp_phy, bool uhbr, bool cr) in __read_delay() argument
291 if (dp_phy == DP_PHY_DPRX) { in __read_delay()
340 enum drm_dp_phy dp_phy, bool uhbr) in drm_dp_read_clock_recovery_delay() argument
347 enum drm_dp_phy dp_phy, bool uhbr) in drm_dp_read_channel_eq_delay() argument
430 if (dp_phy < 0 || dp_phy >= ARRAY_SIZE(phy_names) || in drm_dp_phy_name()
431 WARN_ON(!phy_names[dp_phy])) in drm_dp_phy_name()
434 return phy_names[dp_phy]; in drm_dp_phy_name()
710 enum drm_dp_phy dp_phy, in drm_dp_dpcd_read_phy_link_status() argument
715 if (dp_phy == DP_PHY_DPRX) { in drm_dp_dpcd_read_phy_link_status()
730 DP_LANE0_1_STATUS_PHY_REPEATER(dp_phy), in drm_dp_dpcd_read_phy_link_status()
[all …]
|
| /linux-6.3-rc2/Documentation/devicetree/bindings/display/msm/ |
| A D | dp-controller.yaml | 194 assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;
196 phys = <&dp_phy>;
|
| A D | qcom,sc7180-mdss.yaml | 258 assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;
259 phys = <&dp_phy>;
|
| A D | qcom,sc7280-mdss.yaml | 376 assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;
377 phys = <&dp_phy>;
|
| /linux-6.3-rc2/Documentation/devicetree/bindings/display/bridge/ |
| A D | analogix_dp.txt | 49 phys = <&dp_phy>;
|
| A D | cdns,mhdp8546.yaml | 140 phys = <&dp_phy>;
|
| /linux-6.3-rc2/Documentation/devicetree/bindings/display/rockchip/ |
| A D | analogix_dp-rockchip.txt | 52 phys = <&dp_phy>;
|
| /linux-6.3-rc2/Documentation/devicetree/bindings/display/exynos/ |
| A D | exynos_dp.txt | 84 phys = <&dp_phy>;
|
| /linux-6.3-rc2/drivers/phy/qualcomm/ |
| A D | phy-qcom-qmp-combo.c | 1319 struct phy *dp_phy; member
3350 return qmp->dp_phy; in qmp_combo_phy_xlate()
3430 qmp->dp_phy = devm_phy_create(dev, dp_np, &qmp_combo_dp_phy_ops); in qmp_combo_probe()
3431 if (IS_ERR(qmp->dp_phy)) { in qmp_combo_probe()
3432 ret = PTR_ERR(qmp->dp_phy); in qmp_combo_probe()
3437 phy_set_drvdata(qmp->dp_phy, qmp); in qmp_combo_probe()
|
| /linux-6.3-rc2/arch/arm64/boot/dts/qcom/ |
| A D | sc7180.dtsi | 2742 dp_phy: dp-phy@88ea200 { label
3139 assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;
3140 phys = <&dp_phy>;
3197 <&dp_phy 0>,
3198 <&dp_phy 1>;
|
| A D | sdm845.dtsi | 3935 dp_phy: dp-phy@88ea200 { label
4491 assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;
4492 phys = <&dp_phy>;
4830 <&dp_phy 0>,
4831 <&dp_phy 1>;
|
| A D | sc7280.dtsi | 3355 dp_phy: dp-phy@88ea200 { label
3784 <&dp_phy 0>,
3785 <&dp_phy 1>,
4123 assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;
4124 phys = <&dp_phy>;
|
| /linux-6.3-rc2/arch/arm/boot/dts/ |
| A D | exynos5250.dtsi | 813 dp_phy: video-phy-0 { label
1129 phys = <&dp_phy>;
|
| A D | exynos5420.dtsi | 699 dp_phy: dp-video-phy { label
1215 phys = <&dp_phy>;
|