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Searched refs:dsi_phy_write (Results 1 – 7 of 7) sorted by relevance

/linux-6.3-rc2/drivers/gpu/drm/msm/dsi/phy/
A Ddsi_phy_20nm.c15 dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_0, in dsi_20nm_dphy_set_timing()
17 dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_1, in dsi_20nm_dphy_set_timing()
19 dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_2, in dsi_20nm_dphy_set_timing()
22 dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_3, in dsi_20nm_dphy_set_timing()
24 dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_4, in dsi_20nm_dphy_set_timing()
26 dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_5, in dsi_20nm_dphy_set_timing()
28 dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_6, in dsi_20nm_dphy_set_timing()
30 dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_7, in dsi_20nm_dphy_set_timing()
32 dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_8, in dsi_20nm_dphy_set_timing()
34 dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_9, in dsi_20nm_dphy_set_timing()
[all …]
A Ddsi_phy_28nm_8960.c106 dsi_phy_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_1, in dsi_pll_28nm_clk_set_rate()
113 dsi_phy_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_2, in dsi_pll_28nm_clk_set_rate()
120 dsi_phy_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_3, in dsi_pll_28nm_clk_set_rate()
123 dsi_phy_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_6, in dsi_pll_28nm_clk_set_rate()
128 dsi_phy_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_8, in dsi_pll_28nm_clk_set_rate()
208 dsi_phy_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_0, in dsi_pll_28nm_vco_prepare()
328 dsi_phy_write(bytediv->reg, val); in clk_bytediv_set_rate()
374 dsi_phy_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_10, in dsi_28nm_pll_restore_state()
376 dsi_phy_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_9, in dsi_28nm_pll_restore_state()
378 dsi_phy_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_8, in dsi_28nm_pll_restore_state()
[all …]
A Ddsi_phy_7nm.c209 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_SSC_CONTROL, in dsi_pll_ssc_commit()
256 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_OUTDIV, 0x00); in dsi_pll_config_hzindep_reg()
265 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PFILT, 0x29); in dsi_pll_config_hzindep_reg()
266 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PFILT, 0x2f); in dsi_pll_config_hzindep_reg()
267 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_IFILT, 0x2a); in dsi_pll_config_hzindep_reg()
268 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_IFILT, in dsi_pll_config_hzindep_reg()
293 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_CMODE_1, in dsi_pll_commit()
569 dsi_phy_write(phy_base + REG_DSI_7nm_PHY_CMN_CLK_CFG0, in dsi_7nm_pll_restore_state()
811 dsi_phy_write(lane_base + in dsi_phy_hw_v4_0_config_lpcdrx()
814 dsi_phy_write(lane_base + in dsi_phy_hw_v4_0_config_lpcdrx()
[all …]
A Ddsi_phy_28nm.c203 dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_SDM_CFG2, in dsi_pll_28nm_clk_set_rate()
205 dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_SDM_CFG3, in dsi_pll_28nm_clk_set_rate()
514 dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_VREG_CFG, in dsi_28nm_pll_restore_state()
623 dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_0, in dsi_28nm_dphy_set_timing()
625 dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_1, in dsi_28nm_dphy_set_timing()
627 dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_2, in dsi_28nm_dphy_set_timing()
632 dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_4, in dsi_28nm_dphy_set_timing()
634 dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_5, in dsi_28nm_dphy_set_timing()
636 dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_6, in dsi_28nm_dphy_set_timing()
638 dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_7, in dsi_28nm_dphy_set_timing()
[all …]
A Ddsi_phy_10nm.c202 dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_SSC_CONTROL, in dsi_pll_ssc_commit()
221 dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_OUTDIV, 0x00); in dsi_pll_config_hzindep_reg()
232 dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_PFILT, 0x29); in dsi_pll_config_hzindep_reg()
233 dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_IFILT, 0x3f); in dsi_pll_config_hzindep_reg()
251 dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_CMODE, 0x10); in dsi_pll_commit()
386 dsi_phy_write(pll_10nm->slave->phy->base + in dsi_pll_10nm_vco_prepare()
520 dsi_phy_write(phy_base + REG_DSI_10nm_PHY_CMN_CLK_CFG0, in dsi_10nm_pll_restore_state()
743 dsi_phy_write(lane_base + in dsi_phy_hw_v3_0_config_lpcdrx()
746 dsi_phy_write(lane_base + in dsi_phy_hw_v3_0_config_lpcdrx()
782 dsi_phy_write(lane_base + REG_DSI_10nm_PHY_LN_CFG3(i), in dsi_phy_hw_v3_0_lane_settings()
[all …]
A Ddsi_phy_14nm.c298 dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_SSC_PER1, data); in pll_db_commit_ssc()
301 dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_SSC_PER2, data); in pll_db_commit_ssc()
328 dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_TXCLK_EN, 1); in pll_db_commit_common()
344 dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLL_MISC1, 16); in pll_db_commit_common()
346 dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_IE_TRIM, 4); in pll_db_commit_common()
348 dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_IP_TRIM, 4); in pll_db_commit_common()
360 dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_IPTAT_TRIM, 7); in pll_db_commit_common()
378 dsi_phy_write(cmn_base + REG_DSI_14nm_PHY_CMN_CTRL_1, 0); in pll_14nm_software_reset()
970 dsi_phy_write(lane_base + in dsi_14nm_phy_enable()
972 dsi_phy_write(lane_base + in dsi_14nm_phy_enable()
[all …]
A Ddsi_phy.h16 #define dsi_phy_write(offset, data) msm_writel((data), (offset)) macro

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