| /linux-6.3-rc2/Documentation/admin-guide/hw-vuln/ |
| A D | l1tf.rst | 148 'L1D vulnerable' L1D flushing is disabled
373 the hypervisors, i.e. unconditional L1D flushing
386 mitigation, i.e. conditional L1D flushing
395 i.e. conditional L1D flushing.
421 The KVM hypervisor mitigation mechanism, flushing the L1D cache when
466 To avoid the overhead of the default L1D flushing on VMENTER the
479 the kernel, it's only required to enforce L1D flushing on VMENTER.
499 - L1D flushing on VMENTER:
537 SMT control and L1D flushing can be tuned by the command line
572 is an optimization to avoid double L1D flushing.
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| A D | l1d_flush.rst | 38 If the underlying CPU supports L1D flushing in hardware, the hardware
66 **NOTE** : The opt-in of a task for L1D flushing works only when the task's
68 requested L1D flushing is scheduled on a SMT-enabled core the kernel sends
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| /linux-6.3-rc2/Documentation/core-api/ |
| A D | cachetlb.rst | 7 This document describes the cache/tlb flushing interfaces called
17 thinking SMP cache/tlb flushing must be so inefficient, this is in
23 First, the TLB flushing interfaces, since they are the simplest. The
56 Here we are flushing a specific range of (user) virtual
104 Next, we have the cache flushing interfaces. In general, when Linux
126 The cache flushing routines below need only deal with cache flushing
161 Here we are flushing a specific range of (user) virtual
211 Here in these two interfaces we are flushing a specific range
332 optimise for flushing the entire folio of pages instead
333 of flushing one page at a time.
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| /linux-6.3-rc2/drivers/accessibility/speakup/ |
| A D | synth.c | 41 .flushing = 0,
78 if (speakup_info.flushing) { in _spk_do_catch_up()
79 speakup_info.flushing = 0; in _spk_do_catch_up()
199 speakup_info.flushing = 1; in spk_do_flush()
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| A D | speakup_soft.c | 240 if (!synth_buffer_empty() || speakup_info.flushing) in softsynthx_read()
264 if (speakup_info.flushing) { in softsynthx_read()
265 speakup_info.flushing = 0; in softsynthx_read()
361 (!synth_buffer_empty() || speakup_info.flushing)) in softsynth_poll()
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| A D | thread.c | 35 (speakup_info.flushing || in speakup_thread()
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| A D | speakup_apollo.c | 163 if (speakup_info.flushing) { in do_catch_up()
164 speakup_info.flushing = 0; in do_catch_up()
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| A D | speakup_decext.c | 174 if (speakup_info.flushing) { in do_catch_up()
175 speakup_info.flushing = 0; in do_catch_up()
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| A D | speakup_keypc.c | 196 if (speakup_info.flushing) { in do_catch_up()
197 speakup_info.flushing = 0; in do_catch_up()
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| A D | speakup_acntpc.c | 195 if (speakup_info.flushing) { in do_catch_up()
196 speakup_info.flushing = 0; in do_catch_up()
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| A D | speakup_dectlk.c | 249 if (speakup_info.flushing) { in do_catch_up()
250 speakup_info.flushing = 0; in do_catch_up()
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| A D | speakup_decpc.c | 394 if (speakup_info.flushing) { in do_catch_up()
395 speakup_info.flushing = 0; in do_catch_up()
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| A D | speakup_dtlk.c | 209 if (speakup_info.flushing) { in do_catch_up()
210 speakup_info.flushing = 0; in do_catch_up()
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| A D | spk_types.h | 221 int flushing; member
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| /linux-6.3-rc2/drivers/infiniband/hw/mlx4/ |
| A D | mcg.c | 686 } else if (method == IB_SA_METHOD_DELETE_RESP && group->demux->flushing) in mlx4_ib_mcg_work_handler()
941 if (ctx->flushing) in mlx4_ib_mcg_multiplex_handler()
1065 ctx->flushing = 0; in mlx4_ib_mcg_port_init()
1134 cw->ctx->flushing = 0; in mcg_clean_task()
1142 if (ctx->flushing) in mlx4_ib_mcg_port_cleanup()
1145 ctx->flushing = 1; in mlx4_ib_mcg_port_cleanup()
1149 ctx->flushing = 0; in mlx4_ib_mcg_port_cleanup()
1155 ctx->flushing = 0; in mlx4_ib_mcg_port_cleanup()
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| /linux-6.3-rc2/Documentation/x86/ |
| A D | pti.rst | 96 allows us to skip flushing the entire TLB when switching page
119 h. INVPCID is a TLB-flushing instruction which allows flushing
123 flushing a kernel address, we need to flush all PCIDs, so a
124 single kernel address flush will require a TLB-flushing CR3
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| /linux-6.3-rc2/Documentation/ABI/testing/ |
| A D | procfs-diskstats | 40 20 time spent flushing
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| /linux-6.3-rc2/Documentation/block/ |
| A D | writeback_cache_control.rst | 45 worry if the underlying devices need any explicit cache flushing and how
71 driver needs to tell the block layer that it supports flushing caches by
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| /linux-6.3-rc2/drivers/char/xillybus/ |
| A D | xillyusb.c | 141 unsigned int flushing; member
919 chan->flushing = 0; in process_in_opcode()
1143 if (chan->flushing) { in flush_downstream()
1172 chan->flushing = 1; in flush_downstream()
1190 while (chan->flushing) { in flush_downstream()
1192 !chan->flushing || in flush_downstream()
1204 while (chan->flushing) { in flush_downstream()
1211 !chan->flushing || in flush_downstream()
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| /linux-6.3-rc2/include/trace/events/ |
| A D | jbd2.h | 261 __field( unsigned long, flushing )
275 __entry->flushing = stats->rs_flushing;
290 jiffies_to_msecs(__entry->flushing),
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| /linux-6.3-rc2/fs/xfs/ |
| A D | xfs_trans_ail.c | 428 int flushing = 0; in xfsaild_push() local
510 flushing++; in xfsaild_push()
571 } else if (((stuck + flushing) * 100) / count > 90) { in xfsaild_push()
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| /linux-6.3-rc2/fs/ceph/ |
| A D | caps.c | 1410 arg->dirty = flushing; in __prep_cap()
1813 int flushing; in __mark_caps_flushing() local
1820 flushing = ci->i_dirty_caps; in __mark_caps_flushing()
1822 ceph_cap_string(flushing), in __mark_caps_flushing()
1825 ci->i_flushing_caps |= flushing; in __mark_caps_flushing()
1830 cf->caps = flushing; in __mark_caps_flushing()
2121 flushing = ci->i_dirty_caps; in ceph_check_caps()
2128 flushing = 0; in ceph_check_caps()
2171 int flushing = 0; in try_flush_caps() local
2195 flushing = ci->i_dirty_caps; in try_flush_caps()
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| /linux-6.3-rc2/Documentation/admin-guide/device-mapper/ |
| A D | log-writes.rst | 20 to make it easier to detect improper waiting/flushing.
39 Any REQ_FUA requests bypass this flushing mechanism and are logged as soon as
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| /linux-6.3-rc2/Documentation/networking/device_drivers/ethernet/mellanox/mlx5/ |
| A D | devlink.rst | 137 Recover by flushing the tx queue and reset it.
166 Recover (if needed) by flushing the related queue and reset it.
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| /linux-6.3-rc2/arch/arm/mm/ |
| A D | cache-v7.S | 104 bne start_flush_levels @ LoU != 0, start flushing
112 beq start_flush_levels @ start flushing cache levels
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