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Searched refs:gam_regs (Results 1 – 8 of 8) sorted by relevance

/linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dcn10/
A Ddcn10_dpp_cm.c97 struct color_matrices_reg gam_regs; in program_gamut_remap() local
131 &gam_regs); in program_gamut_remap()
141 &gam_regs); in program_gamut_remap()
151 &gam_regs); in program_gamut_remap()
190 struct color_matrices_reg gam_regs; in dpp1_cm_program_color_matrix() local
233 &gam_regs); in dpp1_cm_program_color_matrix()
369 struct xfer_func_reg gam_regs; in dpp1_cm_program_regamma_luta_settings() local
398 struct xfer_func_reg gam_regs; in dpp1_cm_program_regamma_lutb_settings() local
489 &gam_regs); in dpp1_program_input_csc()
522 struct xfer_func_reg gam_regs; in dpp1_program_degamma_lutb_settings() local
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/linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dcn30/
A Ddcn30_dwb_cm.c85 struct dcn3_xfer_func_reg gam_regs; in dwb3_program_ogam_luta_settings() local
87 dwb3_get_reg_field_ogam(dwbc30, &gam_regs); in dwb3_program_ogam_luta_settings()
104 gam_regs.offset_b = REG(DWB_OGAM_RAMA_OFFSET_B); in dwb3_program_ogam_luta_settings()
105 gam_regs.offset_g = REG(DWB_OGAM_RAMA_OFFSET_G); in dwb3_program_ogam_luta_settings()
106 gam_regs.offset_r = REG(DWB_OGAM_RAMA_OFFSET_R); in dwb3_program_ogam_luta_settings()
118 struct dcn3_xfer_func_reg gam_regs; in dwb3_program_ogam_lutb_settings() local
120 dwb3_get_reg_field_ogam(dwbc30, &gam_regs); in dwb3_program_ogam_lutb_settings()
137 gam_regs.offset_b = REG(DWB_OGAM_RAMB_OFFSET_B); in dwb3_program_ogam_lutb_settings()
305 struct color_matrices_reg gam_regs; in dwb3_program_gamut_remap() local
328 &gam_regs); in dwb3_program_gamut_remap()
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A Ddcn30_dpp_cm.c224 struct dcn3_xfer_func_reg gam_regs; in dpp3_program_gamcor_lut() local
262 gam_regs.offset_b = REG(CM_GAMCOR_RAMB_OFFSET_B); in dpp3_program_gamcor_lut()
263 gam_regs.offset_g = REG(CM_GAMCOR_RAMB_OFFSET_G); in dpp3_program_gamcor_lut()
264 gam_regs.offset_r = REG(CM_GAMCOR_RAMB_OFFSET_R); in dpp3_program_gamcor_lut()
284 gam_regs.offset_b = REG(CM_GAMCOR_RAMA_OFFSET_B); in dpp3_program_gamcor_lut()
285 gam_regs.offset_g = REG(CM_GAMCOR_RAMA_OFFSET_G); in dpp3_program_gamcor_lut()
286 gam_regs.offset_r = REG(CM_GAMCOR_RAMA_OFFSET_R); in dpp3_program_gamcor_lut()
293 dpp3_gamcor_reg_field(dpp, &gam_regs); in dpp3_program_gamcor_lut()
323 struct color_matrices_reg gam_regs; in program_gamut_remap() local
357 &gam_regs); in program_gamut_remap()
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A Ddcn30_mpc.c211 struct dcn3_xfer_func_reg gam_regs; in mpc3_program_luta() local
213 mpc3_ogam_get_reg_field(mpc, &gam_regs); in mpc3_program_luta()
230 gam_regs.offset_b = REG(MPCC_OGAM_RAMA_OFFSET_B[mpcc_id]); in mpc3_program_luta()
231 gam_regs.offset_g = REG(MPCC_OGAM_RAMA_OFFSET_G[mpcc_id]); in mpc3_program_luta()
232 gam_regs.offset_r = REG(MPCC_OGAM_RAMA_OFFSET_R[mpcc_id]); in mpc3_program_luta()
244 struct dcn3_xfer_func_reg gam_regs; in mpc3_program_lutb() local
246 mpc3_ogam_get_reg_field(mpc, &gam_regs); in mpc3_program_lutb()
263 gam_regs.offset_b = REG(MPCC_OGAM_RAMB_OFFSET_B[mpcc_id]); in mpc3_program_lutb()
1062 struct color_matrices_reg gam_regs; in program_gamut_remap() local
1096 &gam_regs); in program_gamut_remap()
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A Ddcn30_dpp.c66 struct color_matrices_reg gam_regs; in dpp3_program_post_csc() local
103 gam_regs.masks.csc_c12 = dpp->tf_mask->CM_POST_CSC_C12; in dpp3_program_post_csc()
107 gam_regs.csc_c11_c12 = REG(CM_POST_CSC_C11_C12); in dpp3_program_post_csc()
108 gam_regs.csc_c33_c34 = REG(CM_POST_CSC_C33_C34); in dpp3_program_post_csc()
112 gam_regs.csc_c11_c12 = REG(CM_POST_CSC_B_C11_C12); in dpp3_program_post_csc()
113 gam_regs.csc_c33_c34 = REG(CM_POST_CSC_B_C33_C34); in dpp3_program_post_csc()
120 &gam_regs); in dpp3_program_post_csc()
663 struct dcn3_xfer_func_reg gam_regs; in dpp3_program_blnd_luta_settings() local
665 dcn3_dpp_cm_get_reg_field(dpp, &gam_regs); in dpp3_program_blnd_luta_settings()
691 struct dcn3_xfer_func_reg gam_regs; in dpp3_program_blnd_lutb_settings() local
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/linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dcn20/
A Ddcn20_mpc.c326 struct xfer_func_reg gam_regs; in mpc2_program_lutb() local
328 mpc2_ogam_get_reg_field(mpc, &gam_regs); in mpc2_program_lutb()
330 gam_regs.start_cntl_b = REG(MPCC_OGAM_RAMB_START_CNTL_B[mpcc_id]); in mpc2_program_lutb()
342 gam_regs.region_start = REG(MPCC_OGAM_RAMB_REGION_0_1[mpcc_id]); in mpc2_program_lutb()
343 gam_regs.region_end = REG(MPCC_OGAM_RAMB_REGION_32_33[mpcc_id]); in mpc2_program_lutb()
345 cm_helper_program_xfer_func(mpc20->base.ctx, params, &gam_regs); in mpc2_program_lutb()
353 struct xfer_func_reg gam_regs; in mpc2_program_luta() local
355 mpc2_ogam_get_reg_field(mpc, &gam_regs); in mpc2_program_luta()
369 gam_regs.region_start = REG(MPCC_OGAM_RAMA_REGION_0_1[mpcc_id]); in mpc2_program_luta()
370 gam_regs.region_end = REG(MPCC_OGAM_RAMA_REGION_32_33[mpcc_id]); in mpc2_program_luta()
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A Ddcn20_dpp_cm.c167 struct color_matrices_reg gam_regs; in program_gamut_remap() local
195 gam_regs.csc_c11_c12 = REG(CM_GAMUT_REMAP_C11_C12); in program_gamut_remap()
196 gam_regs.csc_c33_c34 = REG(CM_GAMUT_REMAP_C33_C34); in program_gamut_remap()
198 gam_regs.csc_c11_c12 = REG(CM_GAMUT_REMAP_B_C11_C12); in program_gamut_remap()
199 gam_regs.csc_c33_c34 = REG(CM_GAMUT_REMAP_B_C33_C34); in program_gamut_remap()
205 &gam_regs); in program_gamut_remap()
391 struct xfer_func_reg gam_regs; in dpp20_program_blnd_luta_settings() local
393 dcn20_dpp_cm_get_reg_field(dpp, &gam_regs); in dpp20_program_blnd_luta_settings()
407 gam_regs.region_start = REG(CM_BLNDGAM_RAMA_REGION_0_1); in dpp20_program_blnd_luta_settings()
419 struct xfer_func_reg gam_regs; in dpp20_program_blnd_lutb_settings() local
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/linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dcn32/
A Ddcn32_mpc.c172 struct dcn3_xfer_func_reg gam_regs; in mpc32_program_post1dluta_settings() local
174 mpc32_post1dlut_get_reg_field(mpc30, &gam_regs); in mpc32_program_post1dluta_settings()
176 gam_regs.start_cntl_b = REG(MPCC_MCM_1DLUT_RAMA_START_CNTL_B[mpcc_id]); in mpc32_program_post1dluta_settings()
188 gam_regs.region_start = REG(MPCC_MCM_1DLUT_RAMA_REGION_0_1[mpcc_id]); in mpc32_program_post1dluta_settings()
189 gam_regs.region_end = REG(MPCC_MCM_1DLUT_RAMA_REGION_32_33[mpcc_id]); in mpc32_program_post1dluta_settings()
191 cm_helper_program_gamcor_xfer_func(mpc->ctx, params, &gam_regs); in mpc32_program_post1dluta_settings()
201 struct dcn3_xfer_func_reg gam_regs; in mpc32_program_post1dlutb_settings() local
203 mpc32_post1dlut_get_reg_field(mpc30, &gam_regs); in mpc32_program_post1dlutb_settings()
217 gam_regs.region_start = REG(MPCC_MCM_1DLUT_RAMB_REGION_0_1[mpcc_id]); in mpc32_program_post1dlutb_settings()
218 gam_regs.region_end = REG(MPCC_MCM_1DLUT_RAMB_REGION_32_33[mpcc_id]); in mpc32_program_post1dlutb_settings()
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