| /linux-6.3-rc2/Documentation/devicetree/bindings/clock/ |
| A D | allwinner,sun4i-a10-gates-clk.yaml | 24 - const: allwinner,sun4i-a10-gates-clk
25 - const: allwinner,sun4i-a10-axi-gates-clk
26 - const: allwinner,sun4i-a10-ahb-gates-clk
27 - const: allwinner,sun5i-a10s-ahb-gates-clk
28 - const: allwinner,sun5i-a13-ahb-gates-clk
29 - const: allwinner,sun7i-a20-ahb-gates-clk
30 - const: allwinner,sun6i-a31-ahb1-gates-clk
31 - const: allwinner,sun8i-a23-ahb1-gates-clk
32 - const: allwinner,sun9i-a80-ahb0-gates-clk
33 - const: allwinner,sun9i-a80-ahb1-gates-clk
[all …]
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| A D | allwinner,sun8i-h3-bus-gates-clk.yaml | 4 $id: http://devicetree.org/schemas/clock/allwinner,sun8i-h3-bus-gates-clk.yaml#
23 const: allwinner,sun8i-h3-bus-gates-clk
59 compatible = "allwinner,sun8i-h3-bus-gates-clk";
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| A D | renesas,cpg-mstp-clocks.yaml | 13 The Clock Pulse Generator (CPG) can gate SoC device clocks. The gates are
14 organized in groups of up to 32 gates.
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| A D | st,nomadik.txt | 7 PLLs and clock gates.
34 HCLK nodes: these represent the clock gates on individual
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| A D | alphascale,acc.txt | 4 clock source, setting deviders and clock gates.
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| A D | ingenic,cgu.yaml | 11 typically includes a variety of PLLs, multiplexers, dividers & gates in order
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| A D | microchip,mpfs-clkcfg.yaml | 14 which gates and enables all peripheral clocks.
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| A D | imx8qxp-lpcg.yaml | 14 model to control the clock gates for the peripherals. An LPCG module
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| /linux-6.3-rc2/drivers/clk/mvebu/ |
| A D | common.c | 193 struct clk **gates; member
211 to_clk_gate(__clk_get_hw(ctrl->gates[n])); in clk_gating_get_src()
213 return ctrl->gates[n]; in clk_gating_get_src()
271 ctrl->gates = kcalloc(ctrl->num_gates, sizeof(*ctrl->gates), in mvebu_clk_gating_setup()
273 if (WARN_ON(!ctrl->gates)) in mvebu_clk_gating_setup()
279 ctrl->gates[n] = clk_register_gate(NULL, desc[n].name, parent, in mvebu_clk_gating_setup()
282 WARN_ON(IS_ERR(ctrl->gates[n])); in mvebu_clk_gating_setup()
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| /linux-6.3-rc2/drivers/clk/sunxi/ |
| A D | Makefile | 16 obj-$(CONFIG_CLK_SUNXI_CLOCKS) += clk-simple-gates.o
20 obj-$(CONFIG_CLK_SUNXI_CLOCKS) += clk-sun8i-bus-gates.o
30 obj-$(CONFIG_CLK_SUNXI_PRCM_SUN6I) += clk-sun6i-apb0-gates.o
34 obj-$(CONFIG_CLK_SUNXI_PRCM_SUN8I) += clk-sun6i-apb0-gates.o
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| /linux-6.3-rc2/drivers/clk/ |
| A D | clk-oxnas.c | 30 struct clk_oxnas_gate **gates; member
192 .gates = ox810se_gates,
198 .gates = ox820_gates,
227 data->gates[i]->regmap = regmap; in oxnas_stdclk_probe()
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| /linux-6.3-rc2/net/nfc/nci/ |
| A D | hci.c | 696 const struct nci_hci_gate *gates) in nci_hci_dev_connect_gates() argument
701 r = nci_hci_connect_gate(ndev, gates->dest_host, in nci_hci_dev_connect_gates()
702 gates->gate, gates->pipe); in nci_hci_dev_connect_gates()
705 gates++; in nci_hci_dev_connect_gates()
729 if (ndev->hci_dev->init_data.gates[0].gate != NCI_HCI_ADMIN_GATE) in nci_hci_dev_session_init()
733 ndev->hci_dev->init_data.gates[0].dest_host, in nci_hci_dev_session_init()
734 ndev->hci_dev->init_data.gates[0].gate, in nci_hci_dev_session_init()
735 ndev->hci_dev->init_data.gates[0].pipe); in nci_hci_dev_session_init()
757 ndev->hci_dev->init_data.gates); in nci_hci_dev_session_init()
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| /linux-6.3-rc2/Documentation/devicetree/bindings/i2c/ |
| A D | i2c-gate.yaml | 16 there are no competing masters to consider for gates and therefore there is
17 no arbitration happening for gates.
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| /linux-6.3-rc2/Documentation/devicetree/bindings/mfd/ |
| A D | allwinner,sun8i-a23-prcm.yaml | 32 - allwinner,sun8i-a23-apb0-gates-clk
83 const: allwinner,sun8i-a23-apb0-gates-clk
192 compatible = "allwinner,sun8i-a23-apb0-gates-clk";
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| A D | allwinner,sun6i-a31-prcm.yaml | 32 - allwinner,sun6i-a31-apb0-gates-clk
111 const: allwinner,sun6i-a31-apb0-gates-clk
237 compatible = "allwinner,sun6i-a31-apb0-gates-clk";
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| /linux-6.3-rc2/net/nfc/hci/ |
| A D | core.c | 450 const struct nfc_hci_gate *gates) in hci_dev_connect_gates() argument
455 gates->gate, gates->pipe); in hci_dev_connect_gates()
458 gates++; in hci_dev_connect_gates()
469 if (hdev->init_data.gates[0].gate != NFC_HCI_ADMIN_GATE) in hci_dev_session_init()
473 hdev->init_data.gates[0].gate, in hci_dev_session_init()
474 hdev->init_data.gates[0].pipe); in hci_dev_session_init()
499 hdev->init_data.gates); in hci_dev_session_init()
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| /linux-6.3-rc2/Documentation/driver-api/nfc/ |
| A D | nfc-hci.rst | 38 support proprietary gates. This is the reason why the driver will pass a list
39 of proprietary gates that must be part of the session. HCI will ensure all
40 those gates have pipes connected when the hci device is set up.
41 In case the chip supports pre-opened gates and pseudo-static pipes, the driver
49 implementation, pipes are totally hidden. The public API only knows gates.
50 This is consistent with the driver need to send commands to proprietary gates
96 mode. This must be implemented only if the hardware uses proprietary gates or a
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| /linux-6.3-rc2/security/safesetid/ |
| A D | Kconfig | 8 SafeSetID is an LSM module that gates the setid family of syscalls to
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| /linux-6.3-rc2/drivers/net/ethernet/stmicro/stmmac/ |
| A D | stmmac_tc.c | 996 u32 gates = qopt->entries[i].gate_mask; in tc_setup_taprio() local
1000 if (gates > GENMASK(31 - wid, 0)) in tc_setup_taprio()
1009 gates |= BIT(0); in tc_setup_taprio()
1013 gates &= ~BIT(0); in tc_setup_taprio()
1020 priv->plat->est->gcl[i] = delta_ns | (gates << wid); in tc_setup_taprio()
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| /linux-6.3-rc2/drivers/platform/x86/intel/int3472/ |
| A D | Kconfig | 20 set of discrete GPIOs and power gates.
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| /linux-6.3-rc2/drivers/clk/stm32/ |
| A D | clk-stm32-core.c | 135 const struct stm32_gate_cfg *gate = &data->gates[gate_id]; in stm32_gate_endisable()
161 const struct stm32_gate_cfg *gate = &data->gates[gate_id]; in stm32_gate_disable_unused()
177 const struct stm32_gate_cfg *gate = &data->gates[gate_id]; in stm32_gate_is_enabled()
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| A D | clk-stm32-core.h | 61 const struct stm32_gate_cfg *gates; member
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| /linux-6.3-rc2/Documentation/devicetree/bindings/clock/ti/davinci/ |
| A D | pll.txt | 4 to the PLL itself, this controller also contains bypasses, gates, dividers,
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| A D | da8xx-cfgchip.txt | 5 gates. This document describes the bindings for those clocks.
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| /linux-6.3-rc2/Documentation/driver-api/fpga/ |
| A D | intro.rst | 38 actual hard hardware that gates a bus to a CPU or a soft ("freeze")
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