Searched refs:gb_addr_config_fields (Results 1 – 6 of 6) sorted by relevance
212 adev->gfx.config.gb_addr_config_fields.num_pipes; in fill_gfx9_tiling_info_from_device()214 adev->gfx.config.gb_addr_config_fields.num_banks; in fill_gfx9_tiling_info_from_device()216 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size; in fill_gfx9_tiling_info_from_device()218 adev->gfx.config.gb_addr_config_fields.num_se; in fill_gfx9_tiling_info_from_device()220 adev->gfx.config.gb_addr_config_fields.max_compress_frags; in fill_gfx9_tiling_info_from_device()222 adev->gfx.config.gb_addr_config_fields.num_rb_per_se; in fill_gfx9_tiling_info_from_device()402 ilog2(adev->gfx.config.gb_addr_config_fields.num_se)); in add_gfx9_modifiers()404 ilog2(adev->gfx.config.gb_addr_config_fields.num_banks)); in add_gfx9_modifiers()405 int rb = ilog2(adev->gfx.config.gb_addr_config_fields.num_se) + in add_gfx9_modifiers()406 ilog2(adev->gfx.config.gb_addr_config_fields.num_rb_per_se); in add_gfx9_modifiers()[all …]
708 num_pkrs = adev->gfx.config.gb_addr_config_fields.num_pkrs; in convert_tiling_flags_to_modifier()709 num_pipes = adev->gfx.config.gb_addr_config_fields.num_pipes; in convert_tiling_flags_to_modifier()783 packers = ilog2(adev->gfx.config.gb_addr_config_fields.num_pkrs); in convert_tiling_flags_to_modifier()788 ilog2(adev->gfx.config.gb_addr_config_fields.num_pkrs)); in convert_tiling_flags_to_modifier()794 rb = ilog2(adev->gfx.config.gb_addr_config_fields.num_se) + in convert_tiling_flags_to_modifier()795 ilog2(adev->gfx.config.gb_addr_config_fields.num_rb_per_se); in convert_tiling_flags_to_modifier()797 ilog2(adev->gfx.config.gb_addr_config_fields.num_se)); in convert_tiling_flags_to_modifier()799 ilog2(adev->gfx.config.gb_addr_config_fields.num_banks)); in convert_tiling_flags_to_modifier()
170 struct gb_addr_config gb_addr_config_fields; member
1941 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 << in gfx_v9_0_gpu_early_init()1948 adev->gfx.config.gb_addr_config_fields.num_pipes; in gfx_v9_0_gpu_early_init()1950 adev->gfx.config.gb_addr_config_fields.num_banks = 1 << in gfx_v9_0_gpu_early_init()1955 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 << in gfx_v9_0_gpu_early_init()1960 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 << in gfx_v9_0_gpu_early_init()1965 adev->gfx.config.gb_addr_config_fields.num_se = 1 << in gfx_v9_0_gpu_early_init()1970 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 + in gfx_v9_0_gpu_early_init()
4274 adev->gfx.config.gb_addr_config_fields.num_pkrs = in get_gb_addr_config()4279 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 << in get_gb_addr_config()4284 adev->gfx.config.gb_addr_config_fields.num_pipes; in get_gb_addr_config()4286 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 << in get_gb_addr_config()4289 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 << in get_gb_addr_config()4292 adev->gfx.config.gb_addr_config_fields.num_se = 1 << in get_gb_addr_config()4295 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 + in get_gb_addr_config()
4404 adev->gfx.config.gb_addr_config_fields.num_pkrs = in gfx_v10_0_gpu_early_init()4423 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 << in gfx_v10_0_gpu_early_init()4428 adev->gfx.config.gb_addr_config_fields.num_pipes; in gfx_v10_0_gpu_early_init()4430 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 << in gfx_v10_0_gpu_early_init()4433 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 << in gfx_v10_0_gpu_early_init()4436 adev->gfx.config.gb_addr_config_fields.num_se = 1 << in gfx_v10_0_gpu_early_init()4439 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 + in gfx_v10_0_gpu_early_init()
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