| /linux-6.3-rc2/Documentation/devicetree/bindings/media/ |
| A D | mediatek,mdp3-rsz.yaml | 25 mediatek,gce-client-reg:
35 a client defined in the header include/dt-bindings/gce/<chip>-gce.h.
37 mediatek,gce-events:
40 to gce. The event id is defined in the gce header
41 include/dt-bindings/gce/<chip>-gce.h of each chips.
50 - mediatek,gce-client-reg
51 - mediatek,gce-events
59 #include <dt-bindings/gce/mt8183-gce.h>
64 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x3000 0x1000>;
65 mediatek,gce-events = <CMDQ_EVENT_MDP_RSZ0_SOF>,
[all …]
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| A D | mediatek,mdp3-rdma.yaml | 29 mediatek,gce-client-reg:
39 a client defined in the header include/dt-bindings/gce/<chip>-gce.h.
41 mediatek,gce-events:
44 to gce. The event id is defined in the gce header
45 include/dt-bindings/gce/<chip>-gce.h of each chips.
67 - mediatek,gce-client-reg
68 - mediatek,gce-events
79 #include <dt-bindings/gce/mt8183-gce.h>
86 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x1000 0x1000>;
93 mboxes = <&gce 20 CMDQ_THR_PRIO_LOWEST>,
[all …]
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| A D | mediatek,mdp3-wrot.yaml | 25 mediatek,gce-client-reg:
33 description: The register of client driver can be configured by gce with
35 a client defined in the header include/dt-bindings/gce/<chip>-gce.h.
37 mediatek,gce-events:
40 to gce. The event id is defined in the gce header
41 include/dt-bindings/gce/<chip>-gce.h of each chips.
56 - mediatek,gce-client-reg
57 - mediatek,gce-events
67 #include <dt-bindings/gce/mt8183-gce.h>
74 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>;
[all …]
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| /linux-6.3-rc2/Documentation/devicetree/bindings/soc/mediatek/ |
| A D | mediatek,ccorr.yaml | 25 mediatek,gce-client-reg:
33 description: The register of client driver can be configured by gce with
35 a client defined in the header include/dt-bindings/gce/<chip>-gce.h.
37 mediatek,gce-events:
40 to gce. The event id is defined in the gce header
41 include/dt-bindings/gce/<chip>-gce.h of each chips.
50 - mediatek,gce-client-reg
51 - mediatek,gce-events
59 #include <dt-bindings/gce/mt8183-gce.h>
64 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0xc000 0x1000>;
[all …]
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| A D | mediatek,wdma.yaml | 26 mediatek,gce-client-reg:
34 description: The register of client driver can be configured by gce with
36 a client defined in the header include/dt-bindings/gce/<chip>-gce.h.
38 mediatek,gce-events:
41 to gce. The event id is defined in the gce header
42 include/dt-bindings/gce/<chip>-gce.h of each chips.
57 - mediatek,gce-client-reg
58 - mediatek,gce-events
68 #include <dt-bindings/gce/mt8183-gce.h>
75 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x6000 0x1000>;
[all …]
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| A D | mediatek,mutex.yaml | 54 mediatek,gce-events:
57 to gce. The event id is defined in the gce header
58 include/dt-bindings/gce/<chip>-gce.h of each chips.
61 mediatek,gce-client-reg:
69 description: The register of client driver can be configured by gce with
71 a client defined in the header include/dt-bindings/gce/<chip>-gce.h.
87 #include <dt-bindings/gce/mt8173-gce.h>
99 mediatek,gce-events = <CMDQ_EVENT_MUTEX0_STREAM_EOF>,
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| /linux-6.3-rc2/Documentation/devicetree/bindings/mailbox/ |
| A D | mediatek,gce-mailbox.yaml | 20 - mediatek,mt6779-gce
21 - mediatek,mt8173-gce
22 - mediatek,mt8183-gce
23 - mediatek,mt8186-gce
24 - mediatek,mt8188-gce
25 - mediatek,mt8192-gce
26 - mediatek,mt8195-gce
46 - const: gce
61 const: mediatek,mt8195-gce
78 gce: mailbox@10212000 {
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| /linux-6.3-rc2/Documentation/devicetree/bindings/arm/mediatek/ |
| A D | mediatek,mmsys.yaml | 72 Documentation/devicetree/bindings/mailbox/mediatek,gce-mailbox.yaml
76 mediatek,gce-client-reg:
78 The register of client driver can be configured by gce with 4 arguments
79 defined in this property, such as phandle of gce, subsys id,
82 register which is defined in the gce header
83 include/dt-bindings/gce/<chip>-gce.h.
103 #include <dt-bindings/gce/mt8173-gce.h>
111 mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>,
112 <&gce 1 CMDQ_THR_PRIO_HIGHEST>;
113 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
|
| /linux-6.3-rc2/Documentation/devicetree/bindings/display/mediatek/ |
| A D | mediatek,mdp-rdma.yaml | 42 mediatek,gce-client-reg:
44 The register of display function block to be set by gce. There are 4 arguments,
45 such as gce node, subsys id, offset and register size. The subsys id that is
46 mapping to the register of display function blocks is defined in the gce header
47 include/dt-bindings/gce/<chip>-gce.h of each chips.
63 - mediatek,gce-client-reg
72 #include <dt-bindings/gce/mt8195-gce.h>
86 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x4000 0x1000>;
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| A D | mediatek,postmask.yaml | 47 mediatek,gce-client-reg:
48 description: The register of client driver can be configured by gce with
49 4 arguments defined in this property, such as phandle of gce, subsys id,
51 defined in the header include/dt-bindings/gce/<chip>-gce.h.
69 #include <dt-bindings/gce/mt8192-gce.h>
81 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>;
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| A D | mediatek,wdma.yaml | 47 mediatek,gce-client-reg:
48 description: The register of client driver can be configured by gce with
49 4 arguments defined in this property, such as phandle of gce, subsys id,
51 defined in the header include/dt-bindings/gce/<chip>-gce.h.
70 #include <dt-bindings/gce/mt8173-gce.h>
84 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>;
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| A D | mediatek,ccorr.yaml | 53 mediatek,gce-client-reg:
54 description: The register of client driver can be configured by gce with
55 4 arguments defined in this property, such as phandle of gce, subsys id,
57 defined in the header include/dt-bindings/gce/<chip>-gce.h.
75 #include <dt-bindings/gce/mt8183-gce.h>
87 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>;
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| A D | mediatek,dither.yaml | 50 mediatek,gce-client-reg:
51 description: The register of client driver can be configured by gce with
52 4 arguments defined in this property, such as phandle of gce, subsys id,
54 defined in the header include/dt-bindings/gce/<chip>-gce.h.
72 #include <dt-bindings/gce/mt8183-gce.h>
84 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>;
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| A D | mediatek,dsc.yaml | 41 mediatek,gce-client-reg:
43 The register of client driver can be configured by gce with 4 arguments
44 defined in this property, such as phandle of gce, subsys id,
47 register which is defined in the gce header
48 include/dt-bindings/gce/<chip>-gce.h.
66 #include <dt-bindings/gce/mt8195-gce.h>
78 mediatek,gce-client-reg = <&gce1 SUBSYS_1c00XXXX 0x9000 0x1000>;
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| A D | mediatek,gamma.yaml | 51 mediatek,gce-client-reg:
52 description: The register of client driver can be configured by gce with
53 4 arguments defined in this property, such as phandle of gce, subsys id,
55 defined in the header include/dt-bindings/gce/<chip>-gce.h.
73 #include <dt-bindings/gce/mt8173-gce.h>
85 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x6000 0x1000>;
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| A D | mediatek,aal.yaml | 54 mediatek,gce-client-reg:
55 description: The register of client driver can be configured by gce with
56 4 arguments defined in this property, such as phandle of gce, subsys id,
58 defined in the header include/dt-bindings/gce/<chip>-gce.h.
76 #include <dt-bindings/gce/mt8173-gce.h>
88 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>;
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| A D | mediatek,color.yaml | 59 mediatek,gce-client-reg:
60 description: The register of client driver can be configured by gce with
61 4 arguments defined in this property, such as phandle of gce, subsys id,
63 defined in the header include/dt-bindings/gce/<chip>-gce.h.
81 #include <dt-bindings/gce/mt8173-gce.h>
93 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x3000 0x1000>;
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| A D | mediatek,ovl-2l.yaml | 53 mediatek,gce-client-reg:
54 description: The register of client driver can be configured by gce with
55 4 arguments defined in this property, such as phandle of gce, subsys id,
57 defined in the header include/dt-bindings/gce/<chip>-gce.h.
76 #include <dt-bindings/gce/mt8183-gce.h>
90 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>;
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| A D | mediatek,ovl.yaml | 67 mediatek,gce-client-reg:
68 description: The register of client driver can be configured by gce with
69 4 arguments defined in this property, such as phandle of gce, subsys id,
71 defined in the header include/dt-bindings/gce/<chip>-gce.h.
90 #include <dt-bindings/gce/mt8173-gce.h>
104 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
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| A D | mediatek,rdma.yaml | 80 mediatek,gce-client-reg:
81 description: The register of client driver can be configured by gce with
82 4 arguments defined in this property, such as phandle of gce, subsys id,
84 defined in the header include/dt-bindings/gce/<chip>-gce.h.
103 #include <dt-bindings/gce/mt8173-gce.h>
118 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
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| A D | mediatek,merge.yaml | 66 mediatek,gce-client-reg:
67 description: The register of client driver can be configured by gce with
68 4 arguments defined in this property, such as phandle of gce, subsys id,
70 defined in the header include/dt-bindings/gce/<chip>-gce.h.
|
| /linux-6.3-rc2/arch/arm64/boot/dts/mediatek/ |
| A D | mt8183.dtsi | 9 #include <dt-bindings/gce/mt8183-gce.h>
1781 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
1787 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x1000 0x1000>;
1801 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x3000 0x1000>;
1810 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x4000 0x1000>;
1819 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>;
1830 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x6000 0x1000>;
1845 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x8000 0x1000>;
1855 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>;
1865 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xa000 0x1000>;
[all …]
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| A D | mt8173.dtsi | 14 #include <dt-bindings/gce/mt8173-gce.h>
997 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
1072 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
1082 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>;
1092 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
1102 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>;
1112 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0 0x1000>;
1122 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>;
1132 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>;
1141 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x3000 0x1000>;
[all …]
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| A D | mt8192.dtsi | 9 #include <dt-bindings/gce/mt8192-gce.h>
1282 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
1334 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>;
1345 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x6000 0x1000>;
1357 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x7000 0x1000>;
1367 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>;
1376 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xa000 0x1000>;
1386 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>;
1396 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
1405 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>;
[all …]
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| /linux-6.3-rc2/drivers/net/ethernet/microchip/sparx5/ |
| A D | sparx5_psfp.c | 135 const struct sparx5_psfp_gce *gce; in sparx5_psfp_sg_set() local
167 gce = &sg->gce[i]; in sparx5_psfp_sg_set()
168 ips = sparx5_psfp_ipv_to_ips(gce->ipv); in sparx5_psfp_sg_set()
170 accum_time_interval += gce->interval; in sparx5_psfp_sg_set()
173 ANA_AC_SG_GCL_GS_CONFIG_GATE_STATE_SET(gce->gate_state), in sparx5_psfp_sg_set()
181 spx5_wr(gce->maxoctets, sparx5, ANA_AC_SG_GCL_OCT_CONFIG(i)); in sparx5_psfp_sg_set()
|