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Searched refs:gfx8 (Results 1 – 8 of 8) sorted by relevance

/linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/core/
A Ddc_debug.c141 plane_state->tiling_info.gfx8.num_banks, in pre_surface_trace()
142 plane_state->tiling_info.gfx8.bank_width, in pre_surface_trace()
143 plane_state->tiling_info.gfx8.bank_width_c, in pre_surface_trace()
144 plane_state->tiling_info.gfx8.bank_height, in pre_surface_trace()
146 plane_state->tiling_info.gfx8.tile_aspect, in pre_surface_trace()
148 plane_state->tiling_info.gfx8.tile_split, in pre_surface_trace()
149 plane_state->tiling_info.gfx8.tile_split_c, in pre_surface_trace()
150 plane_state->tiling_info.gfx8.tile_mode, in pre_surface_trace()
151 plane_state->tiling_info.gfx8.tile_mode_c); in pre_surface_trace()
161 plane_state->tiling_info.gfx8.pipe_config, in pre_surface_trace()
[all …]
/linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dce/
A Ddce_mem_input.c103 switch (tiling_info->gfx8.array_mode) { in get_mi_tiling()
451 GRPH_NUM_BANKS, info->gfx8.num_banks, in program_tiling()
452 GRPH_BANK_WIDTH, info->gfx8.bank_width, in program_tiling()
453 GRPH_BANK_HEIGHT, info->gfx8.bank_height, in program_tiling()
455 GRPH_TILE_SPLIT, info->gfx8.tile_split, in program_tiling()
457 GRPH_PIPE_CONFIG, info->gfx8.pipe_config, in program_tiling()
458 GRPH_ARRAY_MODE, info->gfx8.array_mode, in program_tiling()
468 GRPH_NUM_BANKS, info->gfx8.num_banks, in program_tiling()
469 GRPH_BANK_WIDTH, info->gfx8.bank_width, in program_tiling()
472 GRPH_TILE_SPLIT, info->gfx8.tile_split, in program_tiling()
[all …]
/linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dce110/
A Ddce110_mem_input_v.c172 set_reg_field_value(value, info->gfx8.num_banks, in program_tiling()
175 set_reg_field_value(value, info->gfx8.bank_width, in program_tiling()
178 set_reg_field_value(value, info->gfx8.bank_height, in program_tiling()
181 set_reg_field_value(value, info->gfx8.tile_aspect, in program_tiling()
184 set_reg_field_value(value, info->gfx8.tile_split, in program_tiling()
187 set_reg_field_value(value, info->gfx8.tile_mode, in program_tiling()
190 set_reg_field_value(value, info->gfx8.pipe_config, in program_tiling()
193 set_reg_field_value(value, info->gfx8.array_mode, in program_tiling()
209 set_reg_field_value(value, info->gfx8.bank_width_c, in program_tiling()
221 set_reg_field_value(value, info->gfx8.tile_mode_c, in program_tiling()
[all …]
A Ddce110_hw_sequencer.c2023 if (pipe_ctx->plane_state->tiling_info.gfx8.array_mode == DC_ARRAY_LINEAR_GENERAL) in should_enable_fbc()
/linux-6.3-rc2/drivers/gpu/drm/amd/display/amdgpu_dm/
A Damdgpu_dm_plane.c189 tiling_info->gfx8.num_banks = num_banks; in fill_gfx8_tiling_info_from_flags()
190 tiling_info->gfx8.array_mode = in fill_gfx8_tiling_info_from_flags()
192 tiling_info->gfx8.tile_split = tile_split; in fill_gfx8_tiling_info_from_flags()
193 tiling_info->gfx8.bank_width = bankw; in fill_gfx8_tiling_info_from_flags()
194 tiling_info->gfx8.bank_height = bankh; in fill_gfx8_tiling_info_from_flags()
195 tiling_info->gfx8.tile_aspect = mtaspect; in fill_gfx8_tiling_info_from_flags()
196 tiling_info->gfx8.tile_mode = in fill_gfx8_tiling_info_from_flags()
200 tiling_info->gfx8.array_mode = DC_ARRAY_1D_TILED_THIN1; in fill_gfx8_tiling_info_from_flags()
203 tiling_info->gfx8.pipe_config = in fill_gfx8_tiling_info_from_flags()
A Damdgpu_dm.c6426 dc_plane_state->tiling_info.gfx8.array_mode = DC_ARRAY_LINEAR_GENERAL; in dm_validate_stream_and_context()
/linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dce60/
A Ddce60_hw_sequencer.c105 if (pipe_ctx->plane_state->tiling_info.gfx8.array_mode == DC_ARRAY_LINEAR_GENERAL) in dce60_should_enable_fbc()
/linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/
A Ddc_hw_types.h385 } gfx8; member

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